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    Method of processing semiconductor wafer
    1.
    发明授权
    Method of processing semiconductor wafer 有权
    半导体晶片的处理方法

    公开(公告)号：US07902053B2

    公开(公告)日：2011-03-08

    申请号：US12199547

    申请日：2008-08-27

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

    IPC: H01L21/20

    CPC classification number: H01L29/0634 ,  H01L21/26586

    Abstract: Formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed on the semiconductor substrate for at least three times to form all semiconductor layers, of the epitaxial layers. Thereby, impurity concentration profiles of the semiconductor layers can be uniform, and pn junctions can be formed vertically to a wafer surface. Furthermore, the semiconductor layers can each be formed with a narrow width, so that impurity concentrations thereof are increased. With this configuration, high breakdown voltage and low resistance can be achieved.

    Abstract translation: n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻在半导体衬底上交替进行至少三次以形成外延层的所有半导体层。 因此，半导体层的杂质浓度分布可以是均匀的，并且pn结可以垂直于晶片表面形成。 此外，半导体层各自可以形成为窄的宽度，使得其杂质浓度增加。 利用这种结构，可以实现高击穿电压和低电阻。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07777316B2

    公开(公告)日：2010-08-17

    申请号：US12239368

    申请日：2008-09-26

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama ,  Tetsuya Okada

    IPC: H01L23/02 ,  H01L23/34

    CPC classification number: H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/66734 ,  H01L29/7813 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a semiconductor device in which an insulating region surrounding an element region is provided in an end portion of a semiconductor region with a super junction structure. Since a depletion layer in the element region ends in the insulating region, the end portion of the element region is not formed in a curved surface shape. In other words, the depletion layer has no curved surface in which internal electric fields are concentrated. For this reason, there is no need to take a measure to cause the depletion layer to spread in a horizontal direction by proving a terminal region. Since the terminal region is unnecessary, a chip size can be reduced. Alternatively, an area of the element region can be expanded.

    Abstract translation: 提供一种半导体器件，其中在具有超结结构的半导体区域的端部中设置围绕元件区域的绝缘区域。 由于元件区域中的耗尽层在绝缘区域中结束，元件区域的端部不形成为曲面形状。 换句话说，耗尽层没有内部电场集中的曲面。 因此，通过证明终端区域，不需要采取措施使耗尽层在水平方向上扩展。 由于不需要端子区域，因此可以减小芯片尺寸。 或者，可以扩展元件区域的区域。

    Method of manufacturing semiconductor device
    3.
    发明授权
    Method of manufacturing semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US08133788B2

    公开(公告)日：2012-03-13

    申请号：US12567050

    申请日：2009-09-25

    Applicant: Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    Inventor： Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    IPC: H01L21/336

    CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712

    Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

    Abstract translation: 在栅电极的下方设置有n型杂质区。 通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。 因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。 此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

    Semiconductor device and method of processing the same
    4.
    发明授权
    Semiconductor device and method of processing the same 有权
    半导体器件及其加工方法

    公开(公告)号：US08217486B2

    公开(公告)日：2012-07-10

    申请号：US12236348

    申请日：2008-09-23

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

    IPC: H01L27/00 ,  H01L21/20

    CPC classification number: H01L21/76224 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02587 ,  H01L21/02656 ,  H01L21/761 ,  H01L21/764 ,  H01L21/82 ,  H01L21/8222

    Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

    Abstract translation: 提供半导体晶片。 在半导体晶片中，n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻被交替执行至少三次，使得所有半导体层由半导体衬底上的外延层形成。 由此，各个半导体层可以形成为具有减小的宽度。 因此，如果所需的击穿电压相同，则可以增加各个半导体层的掺杂剂浓度，并且可以降低晶片的电阻值。 此外，剩余的空间部分被绝缘层掩埋，使得在外延层的接合表面中可以避免缺陷。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    5.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20100015772A1

    公开(公告)日：2010-01-21

    申请号：US12567050

    申请日：2009-09-25

    Applicant: Yasuyuki SAYAMA ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    Inventor： Yasuyuki SAYAMA ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    IPC: H01L21/336 ,  H01L21/28

    CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712

    Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

    Abstract translation: 在栅电极的下方设置有n型杂质区。 通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。 因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。 此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

    SEMICONDUCTOR DEVICE AND METHOD OF PROCESSING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF PROCESSING THE SAME 有权
    半导体器件及其加工方法

    公开(公告)号：US20090085149A1

    公开(公告)日：2009-04-02

    申请号：US12236348

    申请日：2008-09-23

    Applicant: Hiroyasu Ishida ,  Yasuyuki Sayama

    Inventor： Hiroyasu Ishida ,  Yasuyuki Sayama

    IPC: H01L27/00 ,  H01L21/20

    CPC classification number: H01L21/76224 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02439 ,  H01L21/02494 ,  H01L21/02521 ,  H01L21/02573 ,  H01L21/02587 ,  H01L21/02656 ,  H01L21/761 ,  H01L21/764 ,  H01L21/82 ,  H01L21/8222

    Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

    Abstract translation: 提供半导体晶片。 在半导体晶片中，n型外延层的形成和蚀刻以及p型外延层的形成和蚀刻被交替执行至少三次，使得所有半导体层由半导体衬底上的外延层形成。 由此，各个半导体层可以形成为具有减小的宽度。 因此，如果所需的击穿电压相同，则可以增加各个半导体层的掺杂剂浓度，并且可以降低晶片的电阻值。 此外，剩余的空间部分被绝缘层掩埋，使得在外延层的接合表面中可以避免缺陷。

    Semiconductor device and method of manufacturing the same
    8.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060220122A1

    公开(公告)日：2006-10-05

    申请号：US11373488

    申请日：2006-03-13

    Applicant: Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    Inventor： Yasuyuki Sayama ,  Tetsuya Okada ,  Makoto Oikawa ,  Hiroyasu Ishida ,  Kazunari Kushiyama

    IPC: H01L29/76

    CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66712

    Abstract: An n type impurity region is provided below a gate electrode. By setting a gate length to be less than a depth of a channel region, a side surface of the channel region and a side surface of the n type impurity region adjacent to the channel region form a substantially perpendicular junction surface. Thus, since a depletion layer widens uniformly in a depth direction of a substrate, it is possible to secure a predetermined breakdown voltage. Furthermore, since an interval between the channel regions, above which the gate electrode is disposed, is uniform from its surface to its bottom, it is possible to increase an impurity concentration of the n type impurity region, resulting in an achievement of a low on-resistance.

    Abstract translation: 在栅电极的下方设置有n型杂质区。 通过将栅极长度设置为小于沟道区的深度，沟道区的侧表面和与沟道区相邻的n型杂质区的侧表面形成基本上垂直的接合表面。 因此，由于耗尽层在衬底的深度方向上均匀地变宽，因此可以确保预定的击穿电压。 此外，由于栅极电极上方的沟道区域之间的间隔从表面到底部均匀，所以可以增加n型杂质区域的杂质浓度，导致实现低的导通 -抵抗性。

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