发明授权
- 专利标题: Semiconductor integrated circuit device with a fuse circuit
- 专利标题(中): 具有保险丝电路的半导体集成电路器件
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申请号: US12433529申请日: 2009-04-30
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公开(公告)号: US07910960B2公开(公告)日: 2011-03-22
- 发明人: Asao Nishimura , Syouji Syukuri , Gorou Kitsukawa , Toshio Miyamoto
- 申请人: Asao Nishimura , Syouji Syukuri , Gorou Kitsukawa , Toshio Miyamoto
- 申请人地址: JP Kanagawa
- 专利权人: Renesas Electronics Corporation
- 当前专利权人: Renesas Electronics Corporation
- 当前专利权人地址: JP Kanagawa
- 代理机构: Mattingly & Malur, P.C.
- 主分类号: H01L23/52
- IPC分类号: H01L23/52
摘要:
In a semiconductor integrated circuit device, testing pads (209b) using a conductive layer, such as relocation wiring layers (205) are provided just above or in the neighborhood of terminals like bonding pads (202b) used only for probe inspection at which bump electrodes (208) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.
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