公开(公告)号：US07378333B2

公开(公告)日：2008-05-27

申请号：US11168460

申请日：2005-06-29

申请人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

发明人： Toshiya Satoh ,  Masahiko Ogino ,  Tadanori Segawa ,  Yoshihide Yamaguchi ,  Hiroyuki Tenmei ,  Atsushi Kazama ,  Ichiro Anjo ,  Asao Nishimura

IPC分类号： H01L21/301

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0236 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

摘要： The present invention is a semiconductor device having the semiconductor element obtained by cutting a semiconductor wafer with the electrode pad formed on one side along a scribe line, a semiconductor element protective layer on the semiconductor element which has a opening on the pad, a stress cushioning layer on the layer which has the opening on the pad, a lead wire portion reaching the layer from the electrode pad via the openings, external electrodes on the lead wire portion, and the conductor protective layer on the layers, the layer and the conductor protective layer forming the respective end faces on the end surface of the semiconductor element inside the scribe line and exposing the range from the end face of the end surface to the inside of the scribe line.

摘要翻译： 本发明是一种具有半导体元件的半导体器件，该半导体器件通过沿着划线在一侧形成电极焊盘切割半导体晶片而获得，半导体元件保护层在半导体元件上具有在该焊盘上的开口，应力缓冲 在该焊盘上具有开口的层上的引线部分，经由开口从电极焊盘到达层的引线部分，引线部分上的外部电极和层上的导体保护层，层和导体保护层 层，形成在划线内的半导体元件的端面上的各个端面，并露出从端面的端面到划线的内侧的范围。

公开(公告)号：US20060261494A1

公开(公告)日：2006-11-23

申请号：US11492165

申请日：2006-07-25

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

IPC分类号： H01L23/48

CPC分类号： H01L24/50 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49572 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/50 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599

摘要： A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.

摘要翻译： 半导体器件包括形成有连接端子的半导体芯片，插入在芯片的主表面之间的弹性结构和形成有连接到连接端子的布线的布线基板，以及连接到连接端子的另一端的凸起电极 布线。 连接端子可以在芯片主表面的中心部分或周边部分，并且弹性结构和布线基板都不设置在连接端子的位置处。 树脂体至少密封连接端子和暴露的布线的第一端（引线）。 在连接端子位于芯片主表面的周边部分的方案中，布线基板突出超过布置有连接端子的芯片边界，并且树脂体形状被布线基板的突出部分限制 。

公开(公告)号：US20060115994A1

公开(公告)日：2006-06-01

申请号：US11331220

申请日：2006-01-13

申请人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

发明人： Hanae Shimokawa ,  Tasao Soga ,  Hiroaki Okudaira ,  Toshiharu Ishida ,  Tetsuya Nakatsuka ,  Yoshiharu Inaba ,  Asao Nishimura

IPC分类号： H01L21/00

CPC分类号： H05K1/181 ,  B23K1/0016 ,  B23K35/004 ,  B23K35/007 ,  B23K35/262 ,  B23K2101/40 ,  H01L23/488 ,  H01L23/49811 ,  H01L23/532 ,  H01L24/29 ,  H01L2224/83101 ,  H01L2924/01322 ,  H01L2924/15747 ,  H05K3/3426 ,  H05K3/3463 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T428/12708 ,  Y10T428/12715 ,  H01L2924/00

摘要： Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.

公开(公告)号：US07038322B2

公开(公告)日：2006-05-02

申请号：US10919331

申请日：2004-08-17

申请人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

发明人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC分类号： H01L21/31

CPC分类号： H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

公开(公告)号：US06927489B1

公开(公告)日：2005-08-09

申请号：US09787526

申请日：2000-03-14

申请人： Akihiro Yaguchi ,  Hideo Miura ,  Atsushi Kazama ,  Asao Nishimura

发明人： Akihiro Yaguchi ,  Hideo Miura ,  Atsushi Kazama ,  Asao Nishimura

IPC分类号： H01L23/12 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

摘要： In a small semiconductor device having external terminals on a semiconductor element and a semiconductor module mounted with the small semiconductor device, disconnection of the external terminals is prevented when a temperature change occurs under the conditions that the semiconductor device is mounted on a printed circuit board. To achieve this a projection is formed on a land which is an external terminal bonding area of the semiconductor device, and a protruded portion of the projection is bonded to the external terminal. An intervening portion of a protective film made of resin material is formed between the lands and semiconductor element.

摘要翻译： 在半导体元件上具有外部端子的小半导体器件和安装有小型半导体器件的半导体模块中，在半导体器件安装在印刷电路板上的条件下发生温度变化时，可防止外部端子断开。 为了实现这一点，在作为半导体器件的外部端子接合区域的焊盘上形成突起，突起的突出部分接合到外部端子。 在平台和半导体元件之间形成由树脂材料构成的保护膜的中间部分。

公开(公告)号：US06861742B2

公开(公告)日：2005-03-01

申请号：US10046446

申请日：2002-01-16

申请人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

发明人： Toshio Miyamoto ,  Ichiro Anjo ,  Asao Nishimura ,  Mitsuaki Katagiri ,  Yuji Shirai ,  Yoshihide Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/66 ,  H01L21/822 ,  H01L23/12 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/538 ,  H01L27/04

CPC分类号： H01L22/22 ,  H01L23/3114 ,  H01L23/5382 ,  H01L24/13 ,  H01L2223/54406 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/11 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2224/05171

摘要： A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

摘要翻译： 半导体集成电路器件包括半导体衬底，形成在半导体衬底的一个主表面上并构成具有多个功能或多个特性的集成电路的电路元件，连接到集成电路的内部连接端子，用于 选择所述集成电路中的多种功能或特性之一，覆盖所述内部连接端子以使得内部连接端子被选择性地暴露的绝缘层和布置在所述绝缘层上的外部连接端子。 通过内部连接端子和外部连接端子之间的连接状态来选择多个功能中的一个或多个特性之一。

公开(公告)号：US20050029674A1

公开(公告)日：2005-02-10

申请号：US10919331

申请日：2004-08-17

申请人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

发明人： Atsushi Kazama ,  Akihiro Yaguchi ,  Hideo Miura ,  Asao Nishimura

IPC分类号： H01L23/31 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L23/3157 ,  H01L23/3114 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/1005 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

摘要翻译： 多芯片模块具有至少两个半导体芯片。 每个半导体芯片具有半导体芯片的芯片电极，用于与芯片电极电连接的导电互连，用于与互连电连接的导电焊盘，设置在焊盘上的外部端子以及介于两者之间的应力松弛层 土地和半导体芯片。 半导体芯片通过外部端子放置在安装板上。 第一半导体芯片的应力松弛层厚于第二半导体芯片的应力松弛层，该第二半导体芯片的距离其中心至位于其最外端部分的外部端子的距离小于第一半导体芯片的应力松弛层。

公开(公告)号：US20050006751A1

公开(公告)日：2005-01-13

申请号：US10909402

申请日：2004-08-03

申请人： Hiroya Shimizu ,  Asao Nishimura ,  Toshiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

发明人： Hiroya Shimizu ,  Asao Nishimura ,  Toshiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

IPC分类号： H01L21/3205 ,  H01L21/60 ,  H01L21/822 ,  H01L23/50 ,  H01L23/52 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L27/04 ,  H01L27/14

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device including a semiconductor element having external terminals at a first level and external electrodes at a second level, higher than the first level. The external terminals include power terminals, ground terminals and signal terminals formed on a main surface of the semiconductor element. The external electrodes include power electrodes connected to the power terminals via power connecting sections, ground electrodes connected to the ground terminals via ground connecting sections and signal electrodes connected to the signal terminals via signal connecting sections. One of the signal terminals, signal electrodes and corresponding signal connecting sections are surrounded by either the power connecting sections connecting the power terminals and power electrodes or by the ground connection sections connecting the ground terminals and ground electrodes.

摘要翻译： 一种半导体器件，包括具有第一电平的外部端子和高于第一电平的第二电平的外部电极的半导体元件。 外部端子包括形成在半导体元件的主表面上的电源端子，接地端子和信号端子。 外部电极包括通过电源连接部分连接到电源端子的电力电极，经由接地连接部分连接到接地端子的接地电极和经由信号连接部分连接到信号端子的信号电极。 信号端子，信号电极和相应的信号连接部分之一被连接电源端子和电源电极的电源连接部分或连接接地端子和接地电极的接地连接部分包围。

公开(公告)号：US06770547B1

公开(公告)日：2004-08-03

申请号：US09698186

申请日：2000-10-30

申请人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

发明人： Kosuke Inoue ,  Hiroyuki Tenmei ,  Yoshihide Yamaguchi ,  Noriyuki Oroku ,  Hiroshi Hozoji ,  Shigeharu Tsunoda ,  Madoka Minagawa ,  Naoya Kanda ,  Ichiro Anjo ,  Asao Nishimura ,  Akira Yajima ,  Kenji Ujiie

IPC分类号： H01L2120

CPC分类号： H01L23/3157 ,  H01L21/563 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3114 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/06102 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01033 ,  H01L2924/01034

摘要： A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.

摘要翻译： 一种半导体装置，其中可以在没有任何底部填充的情况下进行倒装芯片接合，并且其包括半导体器件，通过掩模印刷含有颗粒的电绝缘材料在半导体器件上形成的电绝缘层，以及形成在电学上的外部连接端子 绝缘层并与半导体器件的电极电连接。

公开(公告)号：US06670215B2

公开(公告)日：2003-12-30

申请号：US10058319

申请日：2002-01-30

申请人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

发明人： Chuichi Miyazaki ,  Yukiharu Akiyama ,  Masanori Shibamoto ,  Tomoaki Kudaishi ,  Ichiro Anjoh ,  Kunihiko Nishi ,  Asao Nishimura ,  Hideki Tanaka ,  Ryosuke Kimoto ,  Kunihiro Tsubosaki ,  Akio Hasebe

IPC分类号： H01L2144

CPC分类号： H01L23/49816 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/50 ,  H01L2224/73215 ,  H01L2224/85951 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  Y10T29/4913 ,  Y10T29/49169 ,  H01L2924/20753 ,  H01L2224/05599

摘要： A ball grid array type semiconductor package includes a semiconductor chip formed with bonding pads, an elastomer bonded to the semiconductor chip, a flexible wiring substrate bonded to the elastomer and formed with wirings connected at one end of the bonding pads of the semiconductor chip, a solder resist formed on the main surface of the flexible wiring substrate and solder bump electrodes connected to the other ends of the wirings. The elastomer is bonded to the flexible wiring substrate on the side of the tape, the solder resist is formed on the side of the wirings, and the solder bump electrodes are connected with the wirings by way of through holes formed in the solder resist.