发明授权
- 专利标题: Self-aligned cell integration scheme
- 专利标题(中): 自对准单元集成方案
-
申请号: US11312849申请日: 2005-12-20
-
公开(公告)号: US07915122B2公开(公告)日: 2011-03-29
- 发明人: Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
- 申请人: Richard J. Carter , Hemanshu D. Bhatt , Shiqun Gu , Peter A. Burke , James R. B. Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
- 申请人地址: US MA Woburn
- 专利权人: Nantero, Inc.
- 当前专利权人: Nantero, Inc.
- 当前专利权人地址: US MA Woburn
- 代理机构: Wilmer Cutler Pickering Hale and Dorr LLP
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
公开/授权文献
- US20060281256A1 Self-aligned cell integration scheme 公开/授权日:2006-12-14