公开(公告)号：US07915122B2

公开(公告)日：2011-03-29

申请号：US11312849

申请日：2005-12-20

申请人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

发明人： Richard J. Carter ,  Hemanshu D. Bhatt ,  Shiqun Gu ,  Peter A. Burke ,  James R. B. Elmer ,  Sey-Shing Sun ,  Byung-Sung Kwak ,  Verne Hornback

IPC分类号： H01L21/336

CPC分类号： H01L51/0018 ,  B82Y10/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0545 ,  Y10S977/742

摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

摘要翻译： 一种形成自对准逻辑单元的方法。 在底部电极上形成纳米管层。 在纳米管层上形成夹层。 夹层覆盖纳米管层，从而保护纳米管层。 在钳位层上形成电介质层。 蚀刻介电层。 钳位层提供蚀刻停止并保护纳米管层。 用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。 在纳米管层上形成间隔层。 除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。 除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层， 和纳米管层。

公开(公告)号：US07402770B2

公开(公告)日：2008-07-22

申请号：US11270104

申请日：2005-11-09

申请人： Sey-Shing Sun ,  Hemanshu D. Bhatt ,  Peter A. Burke ,  Richard J. Carter

发明人： Sey-Shing Sun ,  Hemanshu D. Bhatt ,  Peter A. Burke ,  Richard J. Carter

IPC分类号： H01H9/00 ,  G11C11/50 ,  H01L21/00 ,  H01L23/58

CPC分类号： G11C13/025 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/0595 ,  Y10S977/724

摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.

摘要翻译： 具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和 第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触 电极通过在选择性地施加电偏压时通过空腔弯曲。

公开(公告)号：US07582566B2

公开(公告)日：2009-09-01

申请号：US12018849

申请日：2008-01-24

申请人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

发明人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

IPC分类号： H01L21/311

CPC分类号： H01L21/76838 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14

摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

摘要翻译： 在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔 的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

公开(公告)号：US20080132065A1

公开(公告)日：2008-06-05

申请号：US12018849

申请日：2008-01-24

申请人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

发明人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

IPC分类号： H01L21/44

CPC分类号： H01L21/76838 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14

摘要： A method for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

摘要翻译： 在集成电路设计中将空隙扩散转向远离通孔的方法包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二导电层之间形成通孔 的集成电路设计，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

公开(公告)号：US07436040B2

公开(公告)日：2008-10-14

申请号：US11323398

申请日：2005-12-29

申请人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

发明人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

IPC分类号： H01L23/58

CPC分类号： H01L21/7682 ,  H01L21/76808 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

摘要翻译： 在集成电路中转移空穴扩散的方法包括以下步骤：在集成电路的第一导电层中形成具有边界的电导体，在电介质层的边界内在第一导电 层和第二导电层，并且在电导体的通孔和边界之间形成槽，用于将电导体中的空隙扩散转移离开通孔。

公开(公告)号：US07361965B2

公开(公告)日：2008-04-22

申请号：US11323400

申请日：2005-12-29

申请人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

发明人： Derryl D. J. Allman ,  Hemanshu D. Bhatt ,  Charles E. May ,  Peter Austin Burke ,  Byung-Sung Kwak ,  Sey-Shing Sun ,  David T. Price ,  David Pritchard

IPC分类号： H01L23/58

CPC分类号： H01L21/76838 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/14

摘要： A method and apparatus for redirecting void diffusion away from vias in an integrated circuit design includes steps of forming an electrical conductor in a first electrically conductive layer of an integrated circuit design, forming a via between a distal end of the electrical conductor and a second electrically conductive layer of the integrated circuit design, and reducing tensile stress in the electrical conductor to divert void diffusion away from the via.

摘要翻译： 用于在集成电路设计中将空隙扩散转向远离通孔的方法和装置包括在集成电路设计的第一导电层中形成电导体的步骤，在电导体的远端和第二电导体之间形成通孔 集成电路设计的导电层，并且减小电导体中的拉伸应力以将空隙扩散转移离开通孔。

公开(公告)号：US20140084363A1

公开(公告)日：2014-03-27

申请号：US13627912

申请日：2012-09-26

申请人： Jeffrey Pearse ,  Prasad Venkatraman ,  James Sellers ,  Hemanshu D. Bhatt

发明人： Jeffrey Pearse ,  Prasad Venkatraman ,  James Sellers ,  Hemanshu D. Bhatt

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7811

摘要： In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

摘要翻译： 在一个实施例中，MOS晶体管形成为具有有源区和端接区。 在终止区域内，形成多个导体以与多个沟槽内的导体电接触。 终端区域中的多个导体形成为基本共面。

公开(公告)号：US07384801B2

公开(公告)日：2008-06-10

申请号：US11811519

申请日：2007-06-11

申请人： Hemanshu D. Bhatt ,  Jan Fure ,  Derryl D. J. Allman

发明人： Hemanshu D. Bhatt ,  Jan Fure ,  Derryl D. J. Allman

IPC分类号： H01L21/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

摘要翻译： 集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。 电感器形成在由IC的绝缘层分离的多个导体层中。 电感器的最大磁通密度的区域优选地位于IC边缘附近。 另外，电感器可以优选地被分段。 可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

公开(公告)号：US07253497B2

公开(公告)日：2007-08-07

申请号：US10614307

申请日：2003-07-02

申请人： Hemanshu D. Bhatt ,  Jan Fure ,  Derryl D. J. Allman

发明人： Hemanshu D. Bhatt ,  Jan Fure ,  Derryl D. J. Allman

IPC分类号： H01L29/00

CPC分类号： H01L28/10 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

摘要翻译： 集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。 电感器形成在由IC的绝缘层分离的多个导体层中。 电感器的最大磁通密度的区域优选地位于IC边缘附近。 另外，电感器可以优选地被分段。 可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

公开(公告)号：US08940199B2

公开(公告)日：2015-01-27

申请号：US14129035

申请日：2011-10-17

申请人： Hemanshu D. Bhatt ,  Sunit D. Tyagi

发明人： Hemanshu D. Bhatt ,  Sunit D. Tyagi

IPC分类号： B29D11/00

CPC分类号： G02B6/0229 ,  B82Y20/00 ,  B82Y40/00 ,  G02B1/005 ,  G02B1/046 ,  G02B1/048 ,  G02B6/02033 ,  G02B6/02309 ,  G02B6/02319 ,  G02B6/02342 ,  G02B6/02376 ,  Y10S977/70 ,  Y10T428/249921

摘要： The present technology provides an illustrative method for preparing fibers with desirable optical characteristics. The method includes providing a fiber that comprises a core layer and a cladding layer located around the core layer. The method further includes applying a nanostructure template to the cladding layer to form one or more photonic nanostructures having nanostructure scales and compressing the core layer to cause the core layer to bulge and form air gaps between the core layer and the one or more photonic nanostructures.

摘要翻译： 本技术提供了制备具有期望光学特性的纤维的说明性方法。 该方法包括提供包括芯层和位于芯层周围的覆层的光纤。 该方法还包括将纳米结构模板施加到包覆层以形成具有纳米结构尺度的一个或多个光子纳米结构，并压缩芯层以使芯层在芯层和一个或多个光子纳米结构之间凸起并形成气隙。