Invention Grant
- Patent Title: Wafer level chip packaging
- Patent Title (中): 晶圆级芯片封装
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Application No.: US11655777Application Date: 2007-01-19
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Publication No.: US07936062B2Publication Date: 2011-05-03
- Inventor: Giles Humpston , Michael J. Nystrom , Vage Oganesian , Yulia Aksenton , Osher Avsian , Robert Burtzlaff , Avi Dayan , Andrey Grinman , Felix Hazanovich , Ilya Hecht , Charles Rosenstein , David Ovrutsky , Mitchell Hayes Reifel
- Applicant: Giles Humpston , Michael J. Nystrom , Vage Oganesian , Yulia Aksenton , Osher Avsian , Robert Burtzlaff , Avi Dayan , Andrey Grinman , Felix Hazanovich , Ilya Hecht , Charles Rosenstein , David Ovrutsky , Mitchell Hayes Reifel
- Applicant Address: IE
- Assignee: Tessera Technologies Ireland Limited
- Current Assignee: Tessera Technologies Ireland Limited
- Current Assignee Address: IE
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L23/12
- IPC: H01L23/12

Abstract:
Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.
Public/Granted literature
- US20070190691A1 Wafer level chip packaging Public/Granted day:2007-08-16
Information query
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