Invention Grant
- Patent Title: System and method for error correction in cache units
- Patent Title (中): 高速缓存单元纠错系统及方法
-
Application No.: US11363150Application Date: 2006-02-28
-
Publication No.: US08065555B2Publication Date: 2011-11-22
- Inventor: Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
- Applicant: Subramaniam Maiyuran , Varghese George , Vladimir Pentkovski , Sanjib Sarkar , Marina Sherman
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
Public/Granted literature
- US20070226589A1 System and method for error correction in cache units Public/Granted day:2007-09-27
Information query
