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公开(公告)号：US08065555B2
公开(公告)日：2011-11-22
申请号：US11363150
申请日：2006-02-28
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译： 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。
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公开(公告)号：US20070226589A1
公开(公告)日：2007-09-27
申请号：US11363150
申请日：2006-02-28
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译： 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。
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公开(公告)号：US06356270B2
公开(公告)日：2002-03-12
申请号：US09053231
申请日：1998-03-31
IPC分类号： G06T160
CPC分类号： G06F9/30043 , G06F9/3824 , G06F12/0875
摘要： The present invention discloses a method and apparatus method for efficient utilization of write-combining buffers for a sequence of non-temporal stores to scattered locations. The method comprises: converting the sequence of non-temporal stores to stores to intermediate buffers; and grouping the stores to intermediate buffers into consecutive non-temporal stores. The consecutive non-temporal stores correspond to adjacent memory locations in the write-combining buffers.
摘要翻译： 本发明公开了一种用于对分散位置的非时间存储序列的写合成缓冲器有效利用的方法和装置方法。 该方法包括：将非时间存储序列转换为存储到中间缓冲器; 并将商店分组到中间缓冲器到连续的非时间商店。 连续的非时间存储对应于写合成缓冲器中的相邻存储器位置。
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公开(公告)号：US06801208B2
公开(公告)日：2004-10-05
申请号：US09750750
申请日：2000-12-27
申请人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
发明人： Jagganath Keshava , Vladimir Pentkovski , Subramaniam Maiyuran , Salvador Palanca , Hsin-Chu Tsai
IPC分类号： G09G536
CPC分类号： G06F3/14 , G06F12/084 , G09G5/001 , G09G5/393 , G09G2330/021 , G09G2350/00
摘要： A system and method for cache sharing. The system is a microprocessor comprising a processor core and a graphics engine, each coupled to a cache memory. The microprocessor also includes a driver to direct how the cache memory is shared by the processor core and the graphics engine. The method comprises receiving a memory request from a graphics application program and determining whether a cache memory that may be shared between a processor core and a cache memory is available to be shared. If the cache memory is available to be shared, a first portion of the cache memory is allocated to the processor core and a second portion of the cache memory is allocated to the graphics engine. The method and microprocessor may be included in a computing device.
摘要翻译： 一种用于缓存共享的系统和方法。 该系统是包括处理器核心和图形引擎的微处理器，每个耦合到高速缓冲存储器。 微处理器还包括一个驱动程序，用于指示高速缓冲存储器如何由处理器核心和图形引擎共享。 该方法包括从图形应用程序接收存储器请求并确定可以在处理器核心和高速缓冲存储器之间共享的高速缓存存储器是否可共享。 如果高速缓冲存储器可用于共享，则高速缓冲存储器的第一部分被分配给处理器核心，高速缓冲存储器的第二部分被分配给图形引擎。 方法和微处理器可以包括在计算设备中。
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5.发明授权
公开(公告)号：US6073210A
公开(公告)日：2000-06-06
申请号：US53377
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
发明人： Salvador Palanca , Vladimir Pentkovski , Subramaniam Maiyuran , Lance Hacking , Roger A. Golliver , Shreekant S. Thakkar
CPC分类号： G06F13/1631 , G06F12/0802
摘要： The present invention discloses a method and apparatus for synchronizing weakly ordered write combining operations. A memory controller has a buffer to service memory accesses. A store fence instruction is dispatched to the memory controller. If the buffer contains at least a data written by at least one of the weakly ordered write combining operations prior to the store fence instruction, then the store fence instruction is blocked until a block in the buffer containing the data is globally observed. If the buffer does not contain any data written by at least one of the write combining operations prior to the store fence instruction, then the store fence instruction is accepted by the memory controller.
摘要翻译： 本发明公开了一种用于使弱顺序的写入组合操作同步的方法和装置。 存储器控制器具有用于服务存储器访问的缓冲器。 存储栏指令被发送到存储器控制器。 如果缓冲区至少包含由存储栏指令之前的弱顺序写入组合操作中的至少一个写入的数据，则存储栅栏指令被阻止，直到包含数据的缓冲区中的块被全局观察到。 如果在存储栏指令之前缓冲器不包含写入组合操作中的至少一个写入的任何数据，则存储器控制器接受存储栅栏指令。
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公开(公告)号：US06643745B1
公开(公告)日：2003-11-04
申请号：US09053383
申请日：1998-03-31
申请人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
发明人： Salvador Palanca , Niranjan L. Cooray , Angad Narang , Vladimir Pentkovski , Steve Tsai , Subramaniam Maiyuran , Jagannath Keshava , Hsien-Hsin Lee , Steve Spangler , Suresh Kuttuva , Praveen Mosur
IPC分类号： G06F1200
CPC分类号： G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897 , G06F2212/6028
摘要： A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
摘要翻译： 公开了一种计算机系统。 计算机系统包括较高级别的缓存，较低级别的缓存，解码指令的解码器以及耦合到解码器的电路。 在一个实施例中，电路响应于单个解码的指令，在较高级别的高速缓存未命中时从外部存储器检索数据并绕过下一级高速缓存。 在另一个实施例中，电路响应于第一解码指令发出从外部存储器的地址检索数据的请求，以将所述数据仅放置在较低级别的高速缓存中，检测到所述地址的第二可缓存解码指令， 表示高级缓存中的数据。
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7.发明授权Method and system for optimizing write combining performance in a shared buffer structure 失效用于优化共享缓冲区结构中的写入组合性能的方法和系统
公开(公告)号：US6122715A
公开(公告)日：2000-09-19
申请号：US053384
申请日：1998-03-31
申请人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
发明人： Salvador Palanca , Vladimir Pentkovski , Niranjan L. Cooray , Subramaniam Maiyuran , Angad Narang
CPC分类号： G06F12/0804
摘要： An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.
摘要翻译： 一种使用写入组合缓冲器优化写入组合操作的装置和方法。 多个控制字段被分配给每个写合并缓冲器。 每个控制字段具有对应于多个写合并状态之一的值。 多个写入组合状态中的第一个响应写入组合操作转换到多个写入组合状态中的第二个。
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公开(公告)号：US06205520B1
公开(公告)日：2001-03-20
申请号：US09053387
申请日：1998-03-31
IPC分类号： G06F1200
CPC分类号： G06F9/3824 , G06F9/3842 , G06F12/0804 , G06F12/0888 , G06F12/0897
摘要： A processor is disclosed. The processor includes a decoder to decode instructions and a circuit, in response to a decoded instruction, detects an incoming write back or write through streaming store instruction that misses a cache and allocates a buffer in write combining mode. The circuit, in response to a second decoded instruction, detects either an uncacheable speculative write combining store instruction or a second write back streaming store or write through streaming store instruction that hits the buffer and merges the second decoded instruction with the buffer.
摘要翻译： 公开了一种处理器。 处理器包括解码器，用于对指令和电路进行解码，响应于解码的指令，通过错过高速缓冲存储器的流存储指令检测进入写回或写入，并以写入合并模式分配缓冲器。 响应于第二解码指令，该电路检测不可缓存的推测写入组合存储指令或第二回写流存储器，或通过命中缓冲器的流存储指令进行写入，并将第二解码指令与缓冲器合并。
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公开(公告)号：US20060036834A1
公开(公告)日：2006-02-16
申请号：US10917582
申请日：2004-08-13
申请人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
发明人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/325
摘要： A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.
摘要翻译： 一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。 更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距 高速缓存访问并增加可以在处理器内执行uop的速率。
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公开(公告)号：US10297001B2
公开(公告)日：2019-05-21
申请号：US14583300
申请日：2014-12-26
申请人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
发明人： Subramaniam Maiyuran , Shubh B. Shah , Ashutosh Garg , Jin Xu , Thomas A. Piazza , Jorge F. Garcia Pabon , Michael K. Dwyer
摘要： Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to fewer hardware resources compared to when the instructions are executing under other operating conditions. The operating conditions may be determined by examining operands used in a given instruction, including the relative magnitudes of the operands and whether the operands may be taken as equal to certain defined values. The floating point instructions may include instructions for an addition operation, a multiplication operation, a compare operation, and/or a fused multiply-add operation.
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