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公开(公告)号：US08065555B2
公开(公告)日：2011-11-22
申请号：US11363150
申请日：2006-02-28
IPC分类号： G06F11/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译： 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。
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公开(公告)号：US20070226589A1
公开(公告)日：2007-09-27
申请号：US11363150
申请日：2006-02-28
IPC分类号： G11C29/00
CPC分类号： G06F11/1064
摘要： A method and a processor may include storing a first set of data in a data array in a cache unit substantially concurrently to reading a second set of data from the data array, and using the second set of data to generate error correction data corresponding to the first set of data. A method or processor may include reading an entry from a cache in a processor and executing two or more error detection mechanisms on the entry substantially concurrently.
摘要翻译： 方法和处理器可以包括将数据阵列中的第一组数据存储在高速缓存单元中，基本上同时从数据阵列读取第二组数据，并且使用第二组数据来生成对应于 第一组数据。 方法或处理器可以包括从处理器中的高速缓存读取条目，并且基本同时地在条目上执行两个或更多个错误检测机制。
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公开(公告)号：US20060036834A1
公开(公告)日：2006-02-16
申请号：US10917582
申请日：2004-08-13
申请人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
发明人： Subramaniam Maiyuran , Peter Smith , Varghese George , Eran Altshuler , Robert Valentine , Zeev Offen , Oded Lempel
IPC分类号： G06F9/30
CPC分类号： G06F9/3808 , G06F9/325
摘要： A trace management architecture to enable the reuse of uops within one or more repeated traces. More particularly, embodiments of the invention relate to a technique to prevent multiple accesses to various functional units within a trace management architecture by reusing traces or sequences of traces that are repeated during a period of operation of the microprocessor, avoiding performance gaps due to multiple trace cache accesses and increasing the rate at which uops can be executed within a processor.
摘要翻译： 一种跟踪管理架构，可以在一个或多个重复轨迹中重新使用uops。 更具体地，本发明的实施例涉及通过重复使用在微处理器的操作期间重复的迹线或迹线序列来防止对跟踪管理架构内的各种功能单元的多次访问的技术，从而避免由于多个跟踪而导致的性能差距 高速缓存访问并增加可以在处理器内执行uop的速率。
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4.发明授权Method and apparatus for mapping address space of integrated programmable devices within host system memory 有权用于映射主机系统存储器内集成可编程设备的地址空间的方法和装置公开(公告)号：US06748512B2
公开(公告)日：2004-06-08
申请号：US09733875
申请日：2000-12-08
IPC分类号： G06F1208
CPC分类号： G06F12/0284 , G06F12/0835
摘要： A Method and Apparatus for Mapping Address Space of Integrated Programmable Devices within Host System Memory is described herein.
摘要翻译： 本文描述了用于映射主机系统存储器内的集成可编程设备的地址空间的方法和装置。
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公开(公告)号：US09727388B2
公开(公告)日：2017-08-08
申请号：US13995340
申请日：2011-12-29
CPC分类号： G06F9/5083 , G06F9/30003 , G06F9/4856
摘要： Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.
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公开(公告)号：US08892861B2
公开(公告)日：2014-11-18
申请号：US13365096
申请日：2012-02-02
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
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公开(公告)号：US08707062B2
公开(公告)日：2014-04-22
申请号：US12706631
申请日：2010-02-16
申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
发明人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
CPC分类号： G06F1/3287 , G06F1/3203 , G06F1/324 , G06F1/3243 , G06F1/3246 , G06F1/3275 , G06F1/3293 , G06F1/3296 , G06F9/4418 , G06F11/1441 , G06F12/084 , G06F12/0875 , G06F2212/281 , G06F2212/305 , G06F2212/314 , G11C7/1072 , Y02B70/123 , Y02B70/126 , Y02B70/32 , Y02D10/152 , Y02D10/172 , Y02D50/20 , Y02P80/11 , Y10T307/305 , Y10T307/406 , Y10T307/582 , Y10T307/826
摘要： For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，处理器包括第一处理器核心，第二处理器核心和高速缓冲存储器。 第一处理器核心是保存第一处理器核心的状态并进入第一处理器核心断电的模式。 第二处理器核心是保存第二处理器核心的状态并进入其中第二处理器核心断电的模式。 当第一个处理器内核关闭电源时，缓存内存将被供电。 第一处理器核心是响应于第一处理器核心转换到第一处理器核心供电的模式来恢复第一处理器核心的保存状态。 第二处理器核心是响应于第二处理器核心转换到第二处理器核心供电的模式来恢复第二处理器核心的保存状态。 还公开了其他实施例。
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8.发明申请公开(公告)号：US20140032950A1
公开(公告)日：2014-01-30
申请号：US14041688
申请日：2013-09-30
申请人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
发明人： Jose P. Allarey , Varghese George , Sanjeev S. Jahagirdar , Oren Lamdan , Ofer Nathan , Tomer Ziv
IPC分类号： G06F1/20
CPC分类号： G06F15/82 , G06F1/08 , G06F1/206 , G06F1/3203 , G06F1/324 , G06F9/06 , G06F9/30145 , G06F15/76 , Y02D10/126 , Y02D10/16
摘要： With the progress toward multi-core processors, each core is can not readily ascertain the status of the other dies with respect to an idle or active status. A proposal for utilizing an interface to transmit core status among multiple cores in a multi-die microprocessor is discussed. Consequently, this facilitates thermal management by allowing an optimal setting for setting performance and frequency based on utilizing each core status.
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公开(公告)号：US20130013909A1
公开(公告)日：2013-01-10
申请号：US13620119
申请日：2012-09-14
CPC分类号： G06F21/57 , G06F1/324 , G06F1/3296 , G06F21/575 , G06F21/70 , G06F21/81 , G06F2221/2101 , Y02D10/126
摘要： A system and method is provided for establishing safe processor operating points. Some embodiments may include a tamper resistant storage element that stores information regarding one or more operating points of an adjustable processor operating parameter. Some embodiments may further include an element to determine what the current processor operating point is of the operating parameter, and an element to compare the current operating point of the operating parameter with the stored information.
摘要翻译： 提供了一种用于建立安全处理器工作点的系统和方法。 一些实施例可以包括防篡改存储元件，其存储关于可调节处理器操作参数的一个或多个操作点的信息。 一些实施例可以进一步包括用于确定当前处理器工作点是操作参数的元件，以及将操作参数的当前操作点与存储的信息进行比较的元件。
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10.发明申请ASYMMETRIC PERFORMANCE MULTICORE ARCHITECTURE WITH SAME INSTRUCTION SET ARCHITECTURE 有权具有相同指令集架构的不对称性能多体建筑公开(公告)号：US20120198207A1
公开(公告)日：2012-08-02
申请号：US13335257
申请日：2011-12-22
IPC分类号： G06F15/76
CPC分类号： G06F15/80 , G06F1/3206 , G06F1/3293 , G06F1/3296 , G06F9/5094 , G06F13/4022 , Y02D10/122 , Y02D10/151 , Y02D10/22
摘要： A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.
摘要翻译： 描述了一种方法，其涉及多核处理器的操作使能的核，使得两个核以相同的指令集支持相应的软件例程，第一核具有更高的性能并且在相同的一组应用供给下消耗比第二个核的更多的功率 电压和工作频率。
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