发明授权
US08097402B2 Using electric-field directed post-exposure bake for double-patterning (D-P)
有权
使用电场定向后曝光烘烤进行双重图案化（D-P）
- 专利标题： Using electric-field directed post-exposure bake for double-patterning (D-P)
- 专利标题（中）： 使用电场定向后曝光烘烤进行双重图案化（D-P）
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申请号： US12415505申请日： 2009-03-31
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公开(公告)号： US08097402B2公开(公告)日： 2012-01-17
- 发明人: Steven Scheer , Mark Somervell
- 申请人： Steven Scheer , Mark Somervell
- 申请人地址： JP
- 专利权人： Tokyo Electron Limited
- 当前专利权人： Tokyo Electron Limited
- 当前专利权人地址： JP
- 主分类号： G03F7/20
- IPC分类号： G03F7/20
摘要：
The invention provides a method of processing a substrate using Double-Patterning (D-P) processing sequences and Electric-Field Enhanced Layers (E-FELs). The D-P processing sequences and E-FELs can be used to create lines, trenches, vias, spacers, contacts, and gate structures using a minimum number of etch processes.