发明授权
US08122317B1 Two-dimensional parity technique to facilitate error detection and correction in memory arrays
有权
二维奇偶校验技术,便于存储器阵列中的错误检测和校正
- 专利标题: Two-dimensional parity technique to facilitate error detection and correction in memory arrays
- 专利标题(中): 二维奇偶校验技术,便于存储器阵列中的错误检测和校正
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申请号: US12163640申请日: 2008-06-27
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公开(公告)号: US08122317B1公开(公告)日: 2012-02-21
- 发明人: Lawrence T. Clark , Karl C. Mohr
- 申请人: Lawrence T. Clark , Karl C. Mohr
- 申请人地址: US AZ Scottsdale
- 专利权人: Arizona Board of Regents for and on behalf of Arizona State University
- 当前专利权人: Arizona Board of Regents for and on behalf of Arizona State University
- 当前专利权人地址: US AZ Scottsdale
- 代理机构: Withrow & Terranova, P.L.L.C.
- 主分类号: H03M13/00
- IPC分类号: H03M13/00
摘要:
The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in columns. A row check bit is provided for each row bundle in each super bundle. Each row check bit provides a parity bit that is derived from the k bits of the corresponding row bundle. A column check bit is provided for each column in each super bundle. Each column check bit provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle.
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