公开(公告)号：US08122317B1

公开(公告)日：2012-02-21

申请号：US12163640

申请日：2008-06-27

申请人： Lawrence T. Clark ,  Karl C. Mohr

发明人： Lawrence T. Clark ,  Karl C. Mohr

IPC分类号： H03M13/00

CPC分类号： H03M13/2909 ,  G06F11/1012

摘要： The present invention is directed to a two-dimensional parity technique for data to be stored in one or more memory arrays, each of which has various rows and columns of cells. A row of bits in a super bundle is referred to as a row bundle. A super bundle includes numerous rows of row bundles, and corresponding bits in each of the row bundles in the super bundle are aligned in columns. A row check bit is provided for each row bundle in each super bundle. Each row check bit provides a parity bit that is derived from the k bits of the corresponding row bundle. A column check bit is provided for each column in each super bundle. Each column check bit provides a parity bit that is derived from each of the bits in the corresponding column in the super bundle.

摘要翻译： 本发明涉及用于存储在一个或多个存储器阵列中的数据的二维奇偶校验技术，每个存储器阵列具有不同的行和列的单元。 超级捆绑中的一行位称为行捆绑。 超级捆绑包包括多行行束，并且超级捆绑中的每个行束中的相应位在列中对齐。 每个超级捆绑包中的每个行捆绑包都提供行检查位。 每行检查位提供从相应行束的k位导出的​​奇偶校验位。 每个超级包中的每列都提供列校验位。 每个列校验位提供从超级组中相应列中的每个位导出的奇偶校验位。

公开(公告)号：US07649216B1

公开(公告)日：2010-01-19

申请号：US12117416

申请日：2008-05-08

申请人： Lawrence T. Clark ,  Karl C. Mohr ,  Keith E. Holbert

发明人： Lawrence T. Clark ,  Karl C. Mohr ,  Keith E. Holbert

IPC分类号： H01L27/10 ,  H01L29/73 ,  H01L29/739

CPC分类号： H01L27/088 ,  H01L23/552 ,  H01L25/0655 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/921 ,  H01L2924/00

摘要： The present invention relates to radiation hardening by design (RHBD), which employs layout and circuit techniques to mitigate the damaging effects of ionizing radiation. Reverse body biasing (RBB) of N-type metal-oxide-semiconductor (NMOS) transistors may be used to counteract the effects of trapped positive charges in isolation oxides due to ionizing radiation. In a traditional MOS integrated circuit, input/output (I/O) circuitry may be powered using an I/O power supply voltage, and core circuitry may be powered using a core power supply voltage, which is between the I/O power supply voltage and ground. However, in one embodiment of the present invention, the core circuitry is powered using a voltage difference between the core power supply voltage and the I/O power supply voltage. The bodies of NMOS transistors in the core circuitry are coupled to ground; therefore, a voltage difference between the core power supply voltage and ground provides RBB.

摘要翻译： 本发明涉及通过设计的辐射硬化（RHBD），其采用布局和电路技术来减轻电离辐射的破坏作用。 可以使用N型金属氧化物半导体（NMOS）晶体管的反向体偏置（RBB）来抵消由于电离辐射而在隔离氧化物中捕获的正电荷的影响。 在传统的MOS集成电路中，可以使用I / O电源电压对输入/输出（I / O）电路供电，并且核心电路可以使用核心电源电压供电，该电源电压位于I / O电源 电压和地面。 然而，在本发明的一个实施例中，核心电路使用核心电源电压和I / O电源电压之间的电压差来供电。 核心电路中的NMOS晶体管的主体耦合到地; 因此，核心电源电压和地之间的电压差提供RBB。