Invention Grant
US08127192B2 Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode
失效
在中断模式下预测处理器设计验证/验证的测试模式生成和仿真中的lwarx和stwcx指令
- Patent Title: Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode
- Patent Title (中): 在中断模式下预测处理器设计验证/验证的测试模式生成和仿真中的lwarx和stwcx指令
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Application No.: US12172628Application Date: 2008-07-14
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Publication No.: US08127192B2Publication Date: 2012-02-28
- Inventor: Sampan Arora , Divya S. Anvekar , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Bhavani Shringari Nanjundiah
- Applicant: Sampan Arora , Divya S. Anvekar , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Bhavani Shringari Nanjundiah
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: VanLeeuwen & VanLeeuwen
- Agent Matthew B. Talpis
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F11/00

Abstract:
During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address.
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