发明授权
US08138055B2 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
有权
具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
- 专利标题： Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
- 专利标题（中）： 具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
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申请号： US12850119申请日： 2010-08-04
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公开(公告)号： US08138055B2公开(公告)日： 2012-03-20
- 发明人: Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
- 申请人： Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
- 申请人地址： DE Munich SG Singapore
- 专利权人： Infineon Technologies AG,Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人： Infineon Technologies AG,Chartered Semiconductor Manufacturing, Ltd.
- 当前专利权人地址： DE Munich SG Singapore
- 代理机构： Slater & Matsil, L.L.P.
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.