公开(公告)号：US08432014B2

公开(公告)日：2013-04-30

申请号：US13588431

申请日：2012-08-17

申请人： Knut Stahrenberg ,  Jin-Ping Han

发明人： Knut Stahrenberg ,  Jin-Ping Han

IPC分类号： H01L21/70

CPC分类号： H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.

摘要翻译： 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。 图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。 在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压 阈值电压具有与第一阈值电压不同的幅度。

公开(公告)号：US08252649B2

公开(公告)日：2012-08-28

申请号：US12341542

申请日：2008-12-22

申请人： Knut Stahrenberg ,  Jin-Ping Han

发明人： Knut Stahrenberg ,  Jin-Ping Han

IPC分类号： H01L21/00

CPC分类号： H01L21/28088 ,  H01L21/2822 ,  H01L21/28229 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/78

摘要： Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a workpiece having a first region and a second region. A composition or a thickness of at least one of a plurality of material layers of the gate material stack is altered in at least the second region. The gate material stack is patterned, forming a first transistor in the first region and forming a second transistor in the second region. Altering the composition or the thickness of the at least one of the plurality of material layers of the gate material stack in at least the second region results in a first transistor having a first threshold voltage and a second transistor having a second threshold voltage, the second threshold voltage having a different magnitude than the first threshold voltage.

摘要翻译： 公开了制造半导体器件的方法及其结构。 在一个实施例中，制造半导体器件的方法包括在具有第一区域和第二区域的工件上形成栅极材料堆叠。 至少在第二区域中改变栅极材料层叠的多个材料层中的至少一个的组成或厚度。 图案化栅极材料堆叠，在第一区域中形成第一晶体管，并在第二区域中形成第二晶体管。 在至少第二区域中改变栅极材料堆叠的多个材料层中的至少一个材料层的组成或厚度导致具有第一阈值电压的第一晶体管和具有第二阈值电压的第二晶体管，第二晶体管具有第二阈值电压 阈值电压具有与第一阈值电压不同的幅度。

公开(公告)号：US08138055B2

公开(公告)日：2012-03-20

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US20110169096A1

公开(公告)日：2011-07-14

申请号：US12687374

申请日：2010-01-14

申请人： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

发明人： Xiangdong Chen ,  Weipeng Li ,  Anda C. Mocuta ,  Dae-Gyu Park ,  Melanie J. Sherony ,  Kenneth J. Stein ,  Haizhou Yin ,  Franck Arnaud ,  Jin-Ping Han ,  Laegu Kang ,  Yong Meng Lee ,  Young Way Teh ,  Voon-Yew Thean ,  Da Zhang

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L29/7843

摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.

摘要翻译： 集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。 该对互补晶体管包括第一晶体管和第二晶体管。 该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。 第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。 第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

公开(公告)号：US07955936B2

公开(公告)日：2011-06-07

申请号：US12172756

申请日：2008-07-14

申请人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

发明人： Yong Siang Tan ,  Chung Woh Lai ,  Jin-Ping Han ,  Henry K. Utomo ,  Judson R. Holt ,  Eric Harley ,  Richard O. Henry ,  Richard J. Murphy

IPC分类号： H01L21/336

CPC分类号： H01L29/1054 ,  H01L21/30608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC1 solution and excess surface portions of the SiGe region are selectively removed. The SC1 etching process can be part of a rework method in which overgrowth regions of SiGe are selectively removed by exposing the SiGe to and SC1 solution maintained at an elevated temperature. The etching process is carried out for a period of time sufficient to remove excess surface portions of SiGe. The SC1 etching process can be carried out at elevated temperatures ranging from about 25° C. to about 65° C.

摘要翻译： 一种制造半导体器件的方法包括形成SiGe区域。 SiGe区可以是嵌入式源极和漏极区域，或者是半导体器件内的压缩SiGe沟道层或其它SiGe区域。 将SiGe区域暴露于SC1溶液，并且选择性地除去SiGe区域的多余表面部分。 SC1蚀刻工艺可以是返工方法的一部分，其中通过暴露SiGe和保持在升高的温度下的SC1溶液来选择性地除去SiGe的过度生长区域。 进行蚀刻处理足以除去SiGe的多余表面部分的一段时间。 SC1蚀刻工艺可以在约25℃至约65℃的升高的温度下进行。

公开(公告)号：US07951664B2

公开(公告)日：2011-05-31

申请号：US12478905

申请日：2009-06-05

申请人： Knut Stahrenberg ,  Jin-Ping Han

发明人： Knut Stahrenberg ,  Jin-Ping Han

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L28/20

摘要： Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region.

摘要翻译： 公开了制造电阻器的方法，制造半导体器件的方法及其结构。 在一个实施例中，一种制造电阻器的方法包括在工件上形成晶体管材料堆叠并构图晶体管材料堆叠，在工件的第一区域中形成晶体管的栅极，并将晶体管材料堆叠的一部分留在一个 工件的第二区域。 在第二区域中去除晶体管材料堆叠的顶部，并且在靠近晶体管的栅极的第一区域中去除工件的顶部，在第一区域中在工件中形成凹陷区域。 在工件的第一区域的凹陷区域和第二区域中的晶体管材料堆叠的一部分上形成半导体材料，在第二区域中形成电阻器。

公开(公告)号：US20110006373A1

公开(公告)日：2011-01-13

申请号：US12884417

申请日：2010-09-17

申请人： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

发明人： Manfred Eller ,  Jiang Yan ,  Jin-Ping Han ,  Alois Gutmann

IPC分类号： H01L27/092 ,  H01L27/088

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： Methods of fabricating transistors and semiconductor devices and structures thereof are disclosed. In one embodiment, a method of fabricating a transistor includes forming a gate dielectric over a workpiece, forming a gate over the gate dielectric, and forming a stress-inducing material over the gate, the gate dielectric, and the workpiece. Sidewall spacers are formed from the stress-inducing material on sidewalls of the gate and the gate dielectric.

摘要翻译： 公开了制造晶体管和半导体器件的方法及其结构。 在一个实施例中，制造晶体管的方法包括在工件上形成栅极电介质，在栅极电介质上形成栅极，并在栅极，栅极电介质和工件上形成应力诱发材料。 侧壁间隔物由栅极和栅极电介质的侧壁上的应力诱导材料形成。

公开(公告)号：US20100308330A1

公开(公告)日：2010-12-09

申请号：US12478905

申请日：2009-06-05

申请人： Knut Stahrenberg ,  Jin-Ping Han

发明人： Knut Stahrenberg ,  Jin-Ping Han

IPC分类号： H01L27/06 ,  H01L21/8238 ,  H01L29/12

CPC分类号： H01L27/0629 ,  H01L21/823814 ,  H01L28/20

摘要： Methods of manufacturing resistors, methods of manufacturing semiconductor devices, and structures thereof are disclosed. In one embodiment, a method of fabricating a resistor includes forming a transistor material stack over a workpiece and patterning the transistor material stack, forming a gate of a transistor in a first region of the workpiece and leaving a portion of the transistor material stack in a second region of the workpiece. A top portion of the transistor material stack is removed in the second region, and a top portion of the workpiece is removed in the first region proximate the gate of the transistor, forming recessed regions in the workpiece in the first region. A semiconductive material is formed in the recessed regions of the workpiece in the first region and over a portion of the transistor material stack in the second region, forming a resistor in the second region.

摘要翻译： 公开了制造电阻器的方法，制造半导体器件的方法及其结构。 在一个实施例中，一种制造电阻器的方法包括在工件上形成晶体管材料堆叠并构图晶体管材料堆叠，在工件的第一区域中形成晶体管的栅极，并将晶体管材料堆叠的一部分留在一个 工件的第二区域。 在第二区域中去除晶体管材料堆叠的顶部，并且在靠近晶体管的栅极的第一区域中去除工件的顶部，在第一区域中在工件中形成凹陷区域。 在工件的第一区域的凹陷区域和第二区域中的晶体管材料堆叠的一部分上形成半导体材料，在第二区域中形成电阻器。

公开(公告)号：US07842592B2

公开(公告)日：2010-11-30

申请号：US11760056

申请日：2007-06-08

申请人： Thomas Dyer ,  Rajendran Krishnasamy ,  Jin-Ping Han ,  Ernst Demm

发明人： Thomas Dyer ,  Rajendran Krishnasamy ,  Jin-Ping Han ,  Ernst Demm

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7845 ,  H01L21/28026 ,  H01L21/28079 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/49 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7848

摘要： There is disclosed a method of applying stress to a channel region underneath a gate of a field-effect-transistor, which includes the gate, a source region, and a drain region. The method includes steps of embedding stressors in the source and drain regions of the FET; forming a stress liner covering the gate and the source and drain regions; removing a portion of the stress liner, the portion of the stress liner being located on top of the gate of the FET; removing at least a substantial portion of the gate of a first gate material and thus creating an opening therein; and filling the opening with a second gate material.

摘要翻译： 公开了一种对包括栅​​极，源极区和漏极区的场效应晶体管的栅极下面的沟道区域施加应力的方法。 该方法包括以下步骤：将应力源嵌入在FET的源极和漏极区域中; 形成覆盖所述栅极和所述源极和漏极区域的应力衬垫; 去除所述应力衬垫的一部分，所述应力衬垫的所述部分位于所述FET的栅极顶部; 去除第一栅极材料的栅极的至少大部分，从而在其中形成开口; 并用第二栅极材料填充开口。

公开(公告)号：US07795107B2

公开(公告)日：2010-09-14

申请号：US12552352

申请日：2009-09-02

申请人： Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

发明人： Roland Hampp ,  Alois Gutmann ,  Jin-Ping Han ,  O Sung Kwon

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7846

摘要： A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

摘要翻译： 在所提供的半导体本体的表面中形成沟槽。 在沟槽中沉积氧化物，并且在氧化物上沉积帽，其中帽和氧化物的组合在半导体本体上赋予机械应力。