公开(公告)号：US08017487B2

公开(公告)日：2011-09-13

申请号：US11399016

申请日：2006-04-05

Applicant: Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

Inventor： Yung Fu Chong ,  Zhijiong Luo ,  Judson Robert Holt

IPC: H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A strained channel transistor structure and methods of forming a semiconductor device are presented. The transistor structure includes a strained channel region having a first semiconductor material with a first natural lattice constant. A gate dielectric layer overlying the strained channel region, a gate electrode overlying the gate dielectric layer and a source region and drain region oppositely adjacent to the strained channel region are provided. One or both of the source region and drain region include a stressor region having a second semiconductor material with a second natural lattice constant different from the first natural lattice constant. The stressor region has graded concentration of a dopant impurity and/or of a stress inducing molecule.

Abstract translation: 提出了应变通道晶体管结构和形成半导体器件的方法。 晶体管结构包括具有第一自然晶格常数的第一半导体材料的应变沟道区。 提供了覆盖应变通道区域的栅极电介质层，覆盖栅极电介质层的栅极电极和与应变通道区域相邻的源极区域和漏极区域。 源极区域和漏极区域中的一个或两个包括具有第二半导体材料的应力区域，其具有与第一自然晶格常数不同的第二自然晶格常数。 应激物区域具有掺杂剂杂质和/或应力诱导分子的渐变浓度。

公开(公告)号：US07939413B2

公开(公告)日：2011-05-10

申请号：US11297522

申请日：2005-12-08

Applicant: Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

Inventor： Yung Fu Chong ,  Zhijiong Luo ,  Joo Chan Kim ,  Brian Joseph Greene ,  Kern Rim

IPC: H01L21/336

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example method comprising the following. We provide a gate structure over a first region in a substrate. The gate structure is comprised of gate dielectric, a gate, and sidewall spacers. We provide isolation regions in the first region spaced from the gate structure; and a channel region in the substrate under the gate structure. We form S/D recesses in the first region in the substrate adjacent to the sidewall spacers. We form S/D stressor regions filling the S/D recesses. The S/D stressor regions can be thicker adjacent to the gate structure than adjacent to the isolation regions; We implant dopant ions into the S/D stressor regions and into the substrate below the S/D stressor regions adjacent to the isolation regions to form upper stressor doped regions.

Abstract translation: 示例性实施例是用于形成具有嵌入的应力源S / D区域（例如，SiGe）的FET的结构和方法，位于与隔离区域相邻的嵌入式S / D区域下方的掺杂层，以及FET上减少的间隔物上的应力衬垫 门。 包括以下的示例性方法。 我们在衬底的第一区域上提供栅极结构。 栅极结构由栅极电介质，栅极和侧壁间隔物组成。 我们提供与栅极结构间隔开的第一区域中的隔离区域; 以及栅极结构下的衬底中的沟道区。 我们在邻近侧壁间隔物的衬底的第一区域中形成S / D凹槽。 形成填充S / D凹槽的S / D应力区域。 与隔离区相邻的S / D应力区可以比栅极结构更厚; 我们将掺杂剂离子注入到S / D应力区域中并进入与隔离区域相邻的S / D应力区域下方的衬底中以形成上部应力源掺杂区域。

公开(公告)号：US07772071B2

公开(公告)日：2010-08-10

申请号：US11383951

申请日：2006-05-17

Applicant: Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

Inventor： Yung Fu Chong ,  Zhijiong Luo ,  Judson Holt

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained channel CMOS transistor structure comprises a source stressor region comprising a source extension stressor region; and a drain stressor region comprising a drain extension stressor region; wherein a strained channel region is formed between the source extension stressor region and the drain extension stressor region, a width of said channel region being defined by adjacent ends of said extension stressor regions.

Abstract translation: 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 应变通道CMOS晶体管结构包括源应力源区域，其包括源延伸应力区域; 和漏极应力区域，包括漏极延伸应力区域; 其中在所述源延伸应力区域和所述漏极延伸应力区域之间形成应变通道区域，所述沟道区域的宽度由所述延伸应力区域的相邻端限定。

公开(公告)号：US20100124809A1

公开(公告)日：2010-05-20

申请号：US12271262

申请日：2008-11-14

Applicant: Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

Inventor： Kuang Kian Ong ,  Sai Hooi Yeong ,  Kin Leong Pey ,  Lap Chan ,  Yung Fu Chong

IPC: H01L21/336 ,  H01L21/265

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

Abstract: A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of the substrate and vacancies are generated in the first region. During the generation of substrate vacancies, the first region remains substantially crystalline. Interstitial species are generated in a second region and second ions are introduced into the second region to capture the interstitial species. Laser annealing is used to activate dopant species in the first region and repair implantation damage in the second region. The defect engineering process creates a vacancy-rich surface region in which source and drain extension regions having high dopant activation and low sheet resistance are created in an MOS device.

Abstract translation: 在结晶半导体衬底中形成浅结区域的方法和具有浅结区域的半导体器件的制造方法包括缺陷工程步骤，其中将第一离子引入到衬底的第一区域中，并且在第一衬底中产生空位 地区。 在产生衬底空位期间，第一区域保持基本上结晶。 在第二区域中产生间质物质，并且将第二离子引入第二区域以捕获间质物质。 激光退火用于激活第一区域中的掺杂物质并修复第二区域中的植入损伤。 缺陷工程过程产生空位丰富的表面区域，其中在MOS器件中产生具有高掺杂剂激活和低薄层电阻的源极和漏极延伸区域。

公开(公告)号：US20090315152A1

公开(公告)日：2009-12-24

申请号：US12144652

申请日：2008-06-24

Applicant: Shyue Seng TAN ,  Lee Wee TEO ,  Yung Fu CHONG ,  Elgin QUEK ,  Sanford CHU

Inventor： Shyue Seng TAN ,  Lee Wee TEO ,  Yung Fu CHONG ,  Elgin QUEK ,  Sanford CHU

IPC: H01L29/32 ,  H01L21/76

CPC classification number: H01L29/66537 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/3223 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/532 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1083 ,  H01L29/32 ,  H01L29/36 ,  H01L29/66477 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.

Abstract translation: 提出了一种形成装置的方法。 该方法包括提供具有第一和第二区域的结构。 在第一和第二区域的至少一部分之间形成扩散阻挡层。 扩散屏障包括减少元件在第一和第二区域之间的扩散的空腔。

公开(公告)号：US07572712B2

公开(公告)日：2009-08-11

申请号：US11561982

申请日：2006-11-21

Applicant: Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

Inventor： Yung Fu Chong ,  Zhijiong Luo ,  Judson R. Holt

IPC: H01L21/76

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/78639

Abstract: Embodiments for FET devices with stress on the channel region by forming stressor regions under the source/drain regions or the channel region and forming a selective strained Si using lateral epitaxy over the stressor regions. In a first example embodiment, a lateral epitaxial layer is formed over a stressor region under a channel region of an FET. In a second example embodiment, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions of an FET. In a third example embodiment, both PFET and NFET devices are formed. In the PFET device, a lateral S/D epitaxial layer is formed over S/D stressor region under the source/drain regions. In the NFET device, the lateral epitaxial layer is formed over a stressor region under a channel region of the NFET.

Abstract translation: 通过在源极/漏极区域或沟道区域之下形成应力区域并且在应力区域上使用横向外延形成选择性应变Si，从而在通道区域上具有应力的FET器件的实施例。 在第一示例性实施例中，在FET的沟道区之下的应力区域上形成横向外延层。 在第二示例性实施例中，在FET的源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在第三示例性实施例中，形成PFET和NFET器件。 在PFET器件中，在源极/漏极区域之下的S / D应力区域上形成横向S / D外延层。 在NFET器件中，横向外延层形成在NFET的沟道区下方的应力区域上。

公开(公告)号：US20090184341A1

公开(公告)日：2009-07-23

申请号：US12009204

申请日：2008-01-17

Applicant: Yung Fu Chong ,  Lee Wee Teo ,  Shyue Seng Tan ,  Chung Foong Tan

Inventor： Yung Fu Chong ,  Lee Wee Teo ,  Shyue Seng Tan ,  Chung Foong Tan

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

Abstract: A method (and semiconductor device) of fabricating a semiconductor device eliminates shallow trench isolation (STI) recess in embedded SiGe p-type field effect transistor (pFET) structures. This increases device performance by improving isolation and decreasing leakage current caused by SiGe facet growth and silicide encroachment at the STI. A mask is selectively formed over the STI and adjacent nFET regions to protect them during formation (e.g., reactive ion etching (RIE)) of the embedded source/drain (S/D) regions of the pFET. The mask also extends over the STI edge by a predetermined distance to cover a portion of the embedded S/D region disposed between the STI and gate structure. This helps protect or isolate the STI region during SiGe layer formation in the defined embedded S/D regions.

Abstract translation: 制造半导体器件的方法（和半导体器件）消除了嵌入式SiGe p型场效应晶体管（pFET）结构中的浅沟槽隔离（STI）凹槽。 这可以通过改善隔离度和降低由SiGe小面生长引起的漏电流和硅化物侵入STI来提高器件性能。 在STI和相邻的nFET区域上选择性地形成掩模以在pFET的嵌入式源极/漏极（S / D）区域的形成期间（例如，反应离子蚀刻（RIE））保护它们。 掩模也在STI边缘上延伸预定距离以覆盖设置在STI和栅极结构之间的嵌入式S / D区域的一部分。 这有助于在定义的嵌入式S / D区域中的SiGe层形成期间保护或隔离STI区域。

公开(公告)号：US07482656B2

公开(公告)日：2009-01-27

申请号：US11421594

申请日：2006-06-01

Applicant: Zhijiong Luo ,  Yung Fu Chong ,  Kevin K Dezfulian ,  Huilong Zhu ,  Judson R Holt

Inventor： Zhijiong Luo ,  Yung Fu Chong ,  Kevin K Dezfulian ,  Huilong Zhu ,  Judson R Holt

IPC: H01L29/76

CPC classification number: H01L29/66628 ,  H01L29/0653 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636

Abstract: Methods of forming a self-aligned, selective semiconductor on insulator (SOI) structure and a related structure are disclosed. In one embodiment, a method includes providing a substrate; forming a gate structure over a channel within the substrate; recessing a portion of the substrate adjacent the channel; forming an insulating layer on a bottom of the recessed portion; and forming a semiconductor material above the insulating layer. An upper surface of the semiconductor material may be sloped. A MOSFET structure may include a substrate; a channel; a source region and a drain region adjacent the channel; a gate structure above the channel and the substrate; a shallow trench isolation (STI) distal from the gate structure; a selectively laid insulating layer in at least one of the source region and the drain region; and an epitaxially grown semiconductor material above the selectively laid insulating layer.

Abstract translation: 公开了形成自对准选择性半导体绝缘体（SOI）结构和相关结构的方法。 在一个实施例中，一种方法包括提供基底; 在所述衬底内的沟道上形成栅极结构; 使靠近通道的衬底的一部分凹陷; 在所述凹部的底部形成绝缘层; 以及在绝缘层上方形成半导体材料。 半导体材料的上表面可以是倾斜的。 MOSFET结构可以包括衬底; 一个渠道 与沟道相邻的源极区域和漏极区域; 在通道和衬底上方的栅极结构; 远离栅极结构的浅沟槽隔离（STI）; 在源极区域和漏极区域中的至少一个中选择性地铺设绝缘层; 以及在选择性铺设的绝缘层上方的外延生长的半导体材料。

公开(公告)号：US07442618B2

公开(公告)日：2008-10-28

申请号：US11182682

申请日：2005-07-16

Applicant: Yung Fu Chong ,  Brian Joseph Greene ,  Siddhartha Panda ,  Nivo Rovedo

Inventor： Yung Fu Chong ,  Brian Joseph Greene ,  Siddhartha Panda ,  Nivo Rovedo

IPC: H01L21/44

CPC classification number: H01L29/7833 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7846 ,  H01L29/7848

Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Abstract translation: 示出了用于形成用于隔离和/或应力衬底的键孔区域的结构和方法。 在第一实施例中，我们在第一开口中的衬底中形成倒置的键孔形沟槽，优选地使用两步蚀刻。 接下来，我们使用在倒置的键孔沟槽的侧壁上绝缘和/或产生应力的材料填充倒置的孔眼沟槽。 在第二实施例中，我们形成与栅极和隔离结构相邻的键孔应力区域。 键孔应力区域在FET的通道区域附近产生应力，以提高FET性能。 应力区域可以用绝缘体或半导体材料填充。

公开(公告)号：US07413961B2

公开(公告)日：2008-08-19

申请号：US11383952

申请日：2006-05-17

Applicant: Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

Inventor： Yung Fu Chong ,  Kevin K. Dezfulian ,  Zhijiong Luo ,  Huilong Zhu

IPC: H01L21/76

CPC classification number: H01L29/7848 ,  H01L21/3065 ,  H01L21/31116 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

Abstract: The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. There is provided a method of forming a strained channel transistor structure on a substrate, comprising the steps of: forming a source stressor recess comprising a deep source recess and a source extension recess; forming a drain stressor recess comprising a deep drain recess and a drain extension recess; and subsequently forming a source stressor in said source stressor recess and a drain stressor in said drain stressor recess. The deep source/drain and source/drain extension stressors are formed by an uninterrupted etch process and an uninterrupted epitaxy process.

Abstract translation: 本发明涉及半导体集成电路。 更具体地但非唯一地，本发明涉及应变通道互补金属氧化物半导体（CMOS）晶体管结构及其制造方法。 提供了一种在衬底上形成应变通道晶体管结构的方法，包括以下步骤：形成包括深源凹槽和源极延伸凹槽的源极应力器凹部; 形成包括深排水凹槽和排水延伸凹槽的排水应力槽; 并且随后在所述源应力器凹部中形成源应力器，以及在所述漏应力器凹部中形成漏应力器。 深源/漏极和源极/漏极延伸应力源通过不间断的蚀刻工艺和不间断的外延工艺形成。