公开(公告)号：US08138055B2

公开(公告)日：2012-03-20

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US20100297818A1

公开(公告)日：2010-11-25

申请号：US12850119

申请日：2010-08-04

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US07800182B2

公开(公告)日：2010-09-21

申请号：US11602117

申请日：2006-11-20

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L23/62

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US20080119019A1

公开(公告)日：2008-05-22

申请号：US11602117

申请日：2006-11-20

申请人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

发明人： Jin-Ping Han ,  Alois Gutmann ,  Roman Knoefler ,  Jiang Yan ,  Chris Stapelmann ,  Jingyu Lian ,  Yung Fu Chong

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.

摘要翻译： 在制造半导体器件的方法中，在包括第一栅极电极材料的pFET区域的衬底上形成第一栅极堆叠。 在pFET区域蚀刻衬底的源/漏区，并且在pFET区域蚀刻第一栅极堆叠的第一栅电极材料。 蚀刻对蚀刻氧化物和/或氮化物材料至少部分选择性，使得nFET区域被氮化物层（和/或第一氧化物层）屏蔽，并且使得pFET区域的间隔结构至少部分保留。 形成源极/漏极凹部，并且通过蚀刻去除第一栅电极材料的至少一部分，以在pFET区域形成栅电极凹部。 SiGe材料在源极/漏极凹槽中以及在pFET区域的栅极电极凹槽中外延生长。 SMT效应由相同的氮化物nFET掩模实现。

公开(公告)号：US07892905B2

公开(公告)日：2011-02-22

申请号：US11195196

申请日：2005-08-02

申请人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

发明人： Kuang Kian Ong ,  Kin Leong Pey ,  King Jien Chui ,  Ganesh Samudra ,  Yee Chia Yeo ,  Yung Fu Chong

IPC分类号： H01L31/0216 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/7624 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  Y10S438/938

摘要： A process for forming a strained channel region for a MOSFET device via formation of adjacent silicon-germanium source/drain regions, has been developed. The process features either blanket deposition of a silicon-germanium layer, or selective growth of a silicon-germanium layer on exposed portions of a source/drain extension region. A laser anneal procedure results in formation of a silicon-germanium source/drain region via consumption of a bottom portion of the silicon-germanium layer and a top portion of the underlying source/drain region. Optimization of the formation of the silicon-germanium source/drain region via laser annealing can be achieved via a pre-amorphization implantation (PAI) procedure applied to exposed portions of the source/drain region prior to deposition of the silicon-germanium layer. Un-reacted top portions of the silicon-germanium layer are selectively removed after the laser anneal procedure.

摘要翻译： 已经开发了通过形成相邻的硅 - 锗源/漏区来形成用于MOSFET器件的应变沟道区的工艺。 该方法的特征在于硅 - 锗层的覆盖沉积，或硅 - 锗层在源极/漏极延伸区域的暴露部分上的选择性生长。 激光退火程序通过消耗硅 - 锗层的底部部分和下面的源极/漏极区域的顶部部分而导致硅 - 锗源极/漏极区域的形成。 通过经由激光退火形成硅 - 锗源/漏区的优化可以通过在沉积硅 - 锗层之前施加到源/漏区的暴露部分的预非晶化注入（PAI）程序来实现。 在激光退火过程之后，硅 - 锗层的未反应顶部被选择性地去除。

公开(公告)号：US07566609B2

公开(公告)日：2009-07-28

申请号：US11164568

申请日：2005-11-29

申请人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

发明人： Zhijiong Luo ,  Yung Fu Chong ,  Huilong Zhu

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7848

摘要： There is provided a method of manufacturing a field effect transistor (FET) that includes the steps of forming a gate structure on a semiconductor substrate, and forming a recess in the substrate and embedding a second semiconductor material in the recess. The gate structure includes a gate dielectric layer, conductive layers and an insulating layer. Forming said gate structure includes a step of recessing the conductive layer in the gate structure, and the steps of recessing the conductive layer and forming the recess in the substrate are performed in a single step. There is also provided a FET device.

摘要翻译： 提供了一种制造场效应晶体管（FET）的方法，该方法包括以下步骤：在半导体衬底上形成栅极结构，并在衬底中形成凹陷并将第二半导体材料嵌入凹槽中。 栅极结构包括栅极电介质层，导电层和绝缘层。 形成所述栅极结构包括使栅极结构中的导电层凹陷的步骤，并且在单个步骤中执行使导电层凹陷并且在衬底中形成凹部的步骤。 还提供了一种FET器件。

公开(公告)号：US20090039388A1

公开(公告)日：2009-02-12

申请号：US11835059

申请日：2007-08-07

申请人： Lee Wee Teo ,  Yung Fu Chong ,  Elgin Kiok Boone Quek ,  Alain Chan

发明人： Lee Wee Teo ,  Yung Fu Chong ,  Elgin Kiok Boone Quek ,  Alain Chan

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second epitaxial layer aligned to a second PFET gate sidewall spacer.

摘要翻译： 一种集成电路系统，包括：提供包括PFET栅极和PFET栅极电介质的PFET器件; 从与第一PFET栅极侧壁间隔物对准的第一外延层形成源极/漏极延伸; 以及从与第二PFET栅极侧壁间隔物对准的第二外延层形成源极/漏极。

公开(公告)号：US20080283934A1

公开(公告)日：2008-11-20

申请号：US12182212

申请日：2008-07-30

申请人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

发明人： Zhijiong Luo ,  Huilong Zhu ,  Yung Fu Chong ,  Hung Y. Ng ,  Kern Rim ,  Nivo Rovedo

IPC分类号： H01L29/78 ,  H01L21/44

CPC分类号： H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance. Substantially L-shaped silicide element may be formed about a source/drain region, which increases the silicon-to-silicide area, and reduces crowding and contact resistance.

摘要翻译： 公开了具有用于接触的大致L形硅化物元件的结构，半导体器件和方法。 基本上L形的硅化物元件尤其降低了接触电阻并且可以允许增加的CMOS电路的密度。 在一个实施例中，该结构包括基本上为L形的硅化物元件，其包括基底构件和延伸构件，其中基底构件至少部分地延伸到浅沟槽隔离（STI）区域中，使得基底构件的基本水平的表面 直接接触STI区域的基本水平的表面; 以及接触基本上L形的硅化物元件的接触。 触点可以包括用于与基底构件和延伸构件的一部分配合的切口区域，这增加了硅化物与接触面积并降低了接触电阻。 可以围绕源极/漏极区域形成基本上L形的硅化物元素，这增加了硅 - 硅化物面积，并且减少了拥挤和接触电阻。

公开(公告)号：US20070293016A1

公开(公告)日：2007-12-20

申请号：US11424076

申请日：2006-06-14

申请人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

发明人： Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Phung T. Nguyen ,  William C. Wille ,  Richard Lindsay ,  Zhao Lun ,  Yung Fu Chong ,  Siddhartha Panda

IPC分类号： H01L21/76

CPC分类号： H01L21/823892 ,  H01L21/76218 ,  H01L21/76232 ,  H01L21/823878

摘要： A semiconductor structure includes a base semiconductor substrate having a doped region located therein, and an epitaxial region located over the doped region. The semiconductor structure also includes a final isolation region located with the doped region and the epitaxial region. The final isolation region has a greater linewidth within the doped region than within the epitaxial region. A method for fabricating the semiconductor structure provides for forming the doped region prior to the epitaxial region. The doped region may be formed with reduced well implant energy and reduced lateral straggle. The final isolation region with the variable linewidth provides a greater effective isolation depth than an actual trench isolation depth.

摘要翻译： 半导体结构包括具有位于其中的掺杂区的基极半导体衬底和位于掺杂区上方的外延区。 半导体结构还包括位于掺杂区和外延区的最后隔离区。 最后的隔离区域在掺杂区域内具有比外延区域内更大的线宽。 制造半导体结构的方法提供了在外延区之前形成掺杂区。 掺杂区域可以形成为具有减少的良好注入能量和减小的横向分层。 具有可变线宽的最终隔离区域提供比实际沟槽隔离深度更大的有效隔离深度。

公开(公告)号：US06566650B1

公开(公告)日：2003-05-20

申请号：US09664418

申请日：2000-09-18

申请人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

发明人： Chang Chaun Hu ,  Kin Leong Pey ,  Yung Fu Chong ,  Chim Wai Kin ,  Pavel Neuzil ,  Lap Chan

IPC分类号： B01D5944

CPC分类号： G01Q60/58 ,  Y10S977/867 ,  Y10S977/875

摘要： One of the limitations to current usage of scanning thermal microscopes arises when one needs to obtain a thermal map of an electrically biased specimen. Current practice is for the conductive parts of the specimen to be passivated to prevent excessive current leakage between the tip and the conductive sample. The present invention eliminates the need for this by coating the probe's microtip with a layer of insulation that is also a good thermal conductor. Examples of both thermocouple and thermistor based probes are given along with processes for their manufacture.

摘要翻译： 当需要获得电偏置样本的热图时，会出现当前使用扫描热显微镜的局限性。 目前的做法是使样品的导电部件被钝化，以防止尖端和导电样品之间的过大的电流泄漏。 本发明通过用也是良好热导体的绝缘层涂覆探针的微尖头来消除对此的需要。 给出了热电偶和基于热敏电阻的探针的实例以及其制造方法。