Invention Grant
US08138055B2 Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
有权
具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
- Patent Title: Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same
- Patent Title (中): 具有pFET与SiGe栅极电极和嵌入式SiGe源极/漏极区域的半导体器件及其制造方法
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Application No.: US12850119Application Date: 2010-08-04
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Publication No.: US08138055B2Publication Date: 2012-03-20
- Inventor: Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
- Applicant: Jin-Ping Han , Alois Gutmann , Roman Knoefler , Jiang Yan , Chris Stapelmann , Jingyu Lian , Yung Fu Chong
- Applicant Address: DE Munich SG Singapore
- Assignee: Infineon Technologies AG,Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee: Infineon Technologies AG,Chartered Semiconductor Manufacturing, Ltd.
- Current Assignee Address: DE Munich SG Singapore
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material of the first gate stack is etched at the pFET region. The etching is at least partially selective against etching oxide and/or nitride materials so that the nFET region is shielded by a nitride layer (and/or a first oxide layer) and so that the spacer structure of the pFET region at least partially remains. Source/drain recesses are formed and at least part of the first gate electrode material is removed by the etching to form a gate electrode recess at the pFET region. A SiGe material is epitaxially grown in the source/drain recesses and in the gate electrode recess at the pFET region. The SMT effect is achieved from the same nitride nFETs mask.
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