发明授权
- 专利标题： Nested and isolated transistors with reduced impedance difference
- 专利标题（中）： 具有降低阻抗差的嵌套和隔离晶体管
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申请号： US12848999申请日： 2010-08-02
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公开(公告)号： US08143651B2公开(公告)日： 2012-03-27
- 发明人: Johnny Widodo , Liang Choo Hsia , James Yong Meng Lee , Wen Zhi Gao , Zhao Lun , Huang Liu , Chung Woh Lai , Shailendra Mishra , Yew Tuck Chow , Fang Chen , Shiang Yang Ong
- 申请人： Johnny Widodo , Liang Choo Hsia , James Yong Meng Lee , Wen Zhi Gao , Zhao Lun , Huang Liu , Chung Woh Lai , Shailendra Mishra , Yew Tuck Chow , Fang Chen , Shiang Yang Ong
- 申请人地址： SG Singapore
- 专利权人： GLOBALFOUNDRIES Singapore Pte. Ltd.
- 当前专利权人： GLOBALFOUNDRIES Singapore Pte. Ltd.
- 当前专利权人地址： SG Singapore
- 代理机构： Horizon IP Pte Ltd
- 主分类号： H01L27/10
- IPC分类号： H01L27/10 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119
摘要：
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.