Embodiments of the invention relate to integrated circuits comprising inputs for receiving an input signal and a plurality of clock signals having a predetermined phase relationship. The integrated circuit may include a plurality of track-and-hold devices and a plurality of slicer devices. Signal outputs of two track-and-hold devices may be coupled to signal inputs of one slicer device, one of the two track-and-hold devices and the slicer device being coupled to a first input configured to receive a first clock signal and the other track-and-hold device being coupled to a second input being configured to receive a second clock signal.