发明授权
US08198930B2 Reducing power-supply-induced jitter in a clock-distribution circuit
有权
降低时钟分配电路中的电源引起的抖动
- 专利标题: Reducing power-supply-induced jitter in a clock-distribution circuit
- 专利标题(中): 降低时钟分配电路中的电源引起的抖动
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申请号: US12913754申请日: 2010-10-27
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公开(公告)号: US08198930B2公开(公告)日: 2012-06-12
- 发明人: Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
- 申请人: Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Park, Vaughan, Fleming & Dowler LLP
- 主分类号: H03H11/26
- IPC分类号: H03H11/26
摘要:
A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.