公开(公告)号：US09412428B2

公开(公告)日：2016-08-09

申请号：US14003722

申请日：2012-03-21

申请人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

发明人： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC分类号： G06F12/00 ,  G11C7/22 ,  G11C29/02

CPC分类号： G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

摘要翻译： 第一定时参考信号和第二定时参考信号被发送到存储器件。 第二定时参考信号相对于第一定时参考信号具有近似的正交相位关系。 从存储装置接收多个串行数据模式。 第一定时参考和第二定时参考的转换确定何时在多个数据模式的位之间发生转换。 当从存储器装置接收到多个数据模式的位之间发生接收转换时相关联的定时指示符。 时间指示器均使用单个采样器进行测量。 基于定时指示器，确定并应用第一定时参考信号的第一占空比调整，第二定时参考信号的第二占空比调整和正交相位调整。

公开(公告)号：US09378786B2

公开(公告)日：2016-06-28

申请号：US14111857

申请日：2012-04-18

申请人： Ian P. Shaeffer ,  Lei Luo

发明人： Ian P. Shaeffer ,  Lei Luo

IPC分类号： G06F13/12 ,  G06F13/00 ,  G11C7/10 ,  G06F13/42

CPC分类号： G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

摘要： In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

摘要翻译： 在说明性实施例中，存储器电路包括用于读和写存储器操作的数据被传送的第一和第二数据路径，以及用于调整施加到其输入的时钟信号的相位的第一和第二混频器电路。 混频器电路交叉耦合，使得第一和第二混频器的输出都可用于第一和第二数据路径。 一个混频器用于提供第一相位调整的时钟信号供操作电路使用，另一个混频器用于提供第二相位调整的时钟信号，供随后的操作使用。

公开(公告)号：US08581920B2

公开(公告)日：2013-11-12

申请号：US12210104

申请日：2008-09-12

申请人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

发明人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

IPC分类号： G09G5/37 ,  G06T1/60

CPC分类号： G06F9/30018 ,  G09G5/363 ,  G09G5/393 ,  G09G2330/021 ,  G09G2330/06

摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

摘要翻译： 描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。 该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。 该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。 在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

公开(公告)号：US20110069782A1

公开(公告)日：2011-03-24

申请号：US12993843

申请日：2009-06-09

申请人： John Michael Wilson ,  Lei Luo

发明人： John Michael Wilson ,  Lei Luo

IPC分类号： H04L27/00

CPC分类号： H04B3/32 ,  H04L25/026

摘要： This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest neighbors,” with values calibrated and used for each particular transmitter-receiver pair. Embodiments are also presented which address crosstalk induced between lines that are not nearest neighbors, such as, for example, for use in a differential signaling system.

摘要翻译： 本公开提供了一种使用电容耦合电路消除以电感为主的串扰的方法; 它还提出了一种用于校准，选择和编程用于耦合的电容值的方法，以便将每个攻击者信号的导数加到每个受害者信号上，从而否定给定接收机否则将会看到的串扰。 在多线总线的上下文中，可以在每对“最近邻”之间使用交叉耦合电路，其中校准并用于每个特定的发射机 - 接收机对的值。 还提出了解决在不是最近邻的线路之间引起的串扰的实施例，例如用于差分信号系统中的串扰。

公开(公告)号：US20100309964A1

公开(公告)日：2010-12-09

申请号：US12809000

申请日：2008-12-19

申请人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

发明人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

IPC分类号： H04B1/38

CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。

公开(公告)号：US10717699B1

公开(公告)日：2020-07-21

申请号：US16845032

申请日：2020-04-09

申请人： Lei Luo ,  Shinan Jiang ,  Yonghuang Luo ,  Han Li ,  Nan Hui

发明人： Lei Luo ,  Shinan Jiang ,  Yonghuang Luo ,  Han Li ,  Nan Hui

IPC分类号： C07C69/94 ,  C07C67/08

摘要： A compound having the formula (I): (I) is disclosed. A method of preparing the compound of formula (I) is also disclosed.

公开(公告)号：US09166650B2

公开(公告)日：2015-10-20

申请号：US12993843

申请日：2009-06-09

申请人： John Michael Wilson ,  Lei Luo

发明人： John Michael Wilson ,  Lei Luo

IPC分类号： H04B3/32 ,  H04L25/02

CPC分类号： H04B3/32 ,  H04L25/026

摘要： This disclosure presents a method of canceling inductance-dominated crosstalk using a capacitive coupling circuit; it also presents a method of calibrating, selecting and programming a capacitance value used for coupling, so as to add a derivative of each aggressor signal to each victim signal, and thereby negate crosstalk that would otherwise be seen by a given receiver. In the context of a multiple-line bus, cross-coupling circuits may be used between each pair of “nearest neighbors,” with values calibrated and used for each particular transmitter-receiver pair. Embodiments are also presented which address crosstalk induced between lines that are not nearest neighbors, such as, for example, for use in a differential signaling system.

摘要翻译： 本公开提供了一种使用电容耦合电路消除以电感为主的串扰的方法; 它还提出了一种用于校准，选择和编程用于耦合的电容值的方法，以便将每个攻击者信号的导数加到每个受害者信号上，从而否定给定接收机否则将会看到的串扰。 在多线总线的上下文中，可以在每对“最近邻”之间使用交叉耦合电路，其中校准并用于每个特定的发射机 - 接收机对的值。 还提出了解决在不是最近邻的线路之间引起的串扰的实施例，例如用于差分信号系统中的串扰。

公开(公告)号：US09046909B2

公开(公告)日：2015-06-02

申请号：US14241843

申请日：2012-08-31

申请人： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

发明人： Brian S. Leibowitz ,  Michael D. Bucher ,  Lei Luo ,  Chaofeng Charlie Huang ,  Amir Amirkhany ,  Huy M. Nguyen ,  Hsuan-Jung (Bruce) Su ,  John Wilson

IPC分类号： G05F1/10 ,  G05F1/46 ,  G11C5/14

CPC分类号： G05F1/462 ,  G11C5/147

摘要： An integrated circuit includes a voltage regulator to supply a regulated voltage and a data output that couples to an unterminated transmission line. The circuit draws a variable amount of power from the voltage regulator according to the data. The voltage regulator includes a first current generation circuit to provide a data transition-dependent current.

摘要翻译： 集成电路包括用于提供调节电压的电压调节器和耦合到未终端传输线的数据输出。 该电路根据数据从电压调节器抽取可变量的功率。 电压调节器包括用于提供数据转变相关电流的第一电流产生电路。

公开(公告)号：US20140281205A1

公开(公告)日：2014-09-18

申请号：US14111857

申请日：2012-04-18

申请人： Ian P. Shaeffer ,  Lei Luo

发明人： Ian P. Shaeffer ,  Lei Luo

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G06F1/08 ,  G06F13/16 ,  G06F13/4068 ,  G06F13/4243 ,  G11C7/1072

摘要： In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

摘要翻译： 在说明性实施例中，存储器电路包括用于读和写存储器操作的数据被传送的第一和第二数据路径，以及用于调整施加到其输入的时钟信号的相位的第一和第二混频器电路。 混频器电路交叉耦合，使得第一和第二混频器的输出都可用于第一和第二数据路径。 一个混频器用于提供第一相位调整的时钟信号供操作电路使用，另一个混频器用于提供第二相位调整的时钟信号，供随后的操作使用。

公开(公告)号：US08498344B2

公开(公告)日：2013-07-30

申请号：US12999495

申请日：2009-06-18

申请人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

发明人： John M. Wilson ,  Aliazam Abbasfar ,  John Eble, III ,  Lei Luo ,  Jade M. Kizer ,  Carl William Werner ,  Wayne Dettloff

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H04L25/49 ,  H04L25/4915

摘要： A data system 102 permits bus encoding based on frequency of the bus; an encoding scheme may be implemented to avoid undesirable frequency conditions such as a resonant condition that may lead to degradation in system performance. The device or integrated circuit will typically include an encoder; in one embodiment, the encoder is a data bus inversion (DBI) circuit that selectively inverts all lines of a data bus. A detector that may include a band-pass or stop-band filter that, for example, evaluates data for transmission on the bus to detect frequency, for example, a predetermined frequency or a frequency range. The detector provides a control signal for the encoder to selectively apply an encoding scheme as a function of frequency.

摘要翻译： 数据系统102允许基于总线频率的总线编码; 可以实现编码方案以避免不期望的频率条件，例如可能导致系统性能下降的共振条件。 设备或集成电路通常将包括编码器; 在一个实施例中，编码器是选择性地反转数据总线的所有行的数据总线反相（DBI）电路。 可以包括带通或阻带滤波器的检测器，其例如评估用于在总线上传输的数据以检测频率，例如预定频率或频率范围。 检测器为编码器提供控制信号，以选择性地应用作为频率的函数的编码方案。