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    Reducing power-supply-induced jitter in a clock-distribution circuit
    1.
    发明授权
    Reducing power-supply-induced jitter in a clock-distribution circuit 有权
    降低时钟分配电路中的电源引起的抖动

    公开(公告)号：US08198930B2

    公开(公告)日：2012-06-12

    申请号：US12913754

    申请日：2010-10-27

    申请人： Jared Zerbe ,  Brian Leibowitz ,  Lei Luo ,  John Wilson ,  Anshuman Bhuyan ,  Marko Aleksic

    发明人： Jared Zerbe ,  Brian Leibowitz ,  Lei Luo ,  John Wilson ,  Anshuman Bhuyan ,  Marko Aleksic

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265 ,  G06F1/10 ,  H03K5/1506 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03K2217/0018

    摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.

    摘要翻译： 描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。 在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。 注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。 该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。 然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。 接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和 第二传播延迟的变化是互补的。

    REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT
    2.
    发明申请
    REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT 有权
    在时钟分配电路中减少供电电感器

    公开(公告)号：US20110102043A1

    公开(公告)日：2011-05-05

    申请号：US12913754

    申请日：2010-10-27

    申请人： Jared Zerbe ,  Brian Leibowitz ,  Lei Luo ,  John Wilson ,  Anshuman Bhuyan ,  Marko Aleksic

    发明人： Jared Zerbe ,  Brian Leibowitz ,  Lei Luo ,  John Wilson ,  Anshuman Bhuyan ,  Marko Aleksic

    IPC分类号： H03H11/26

    CPC分类号： H03H11/265 ,  G06F1/10 ,  H03K5/1506 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03K2217/0018

    摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.

    摘要翻译： 描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。 在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。 注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。 该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。 然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。 接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和 第二传播延迟的变化是互补的。

    Fast power-on bias circuit
    3.
    发明授权
    Fast power-on bias circuit 有权
    快速上电偏置电路

    公开(公告)号：US08618869B2

    公开(公告)日：2013-12-31

    申请号：US13341483

    申请日：2011-12-30

    申请人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

    发明人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

    IPC分类号： G05F1/10

    CPC分类号： G06F1/26 ,  G06F1/3203 ,  H03K17/223

    摘要： Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

    摘要翻译： 常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。 供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。 示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

    FAST POWER-ON BIAS CIRCUIT
    4.
    发明申请
    FAST POWER-ON BIAS CIRCUIT 有权
    快速上电偏置电路

    公开(公告)号：US20120169412A1

    公开(公告)日：2012-07-05

    申请号：US13341483

    申请日：2011-12-30

    申请人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

    发明人： Wayne Dettloff ,  John Wilson ,  Lei Luo ,  Brian Leibowitz ,  Jared Zerbe ,  Pravin Kumar Venkatesan

    IPC分类号： G05F3/08

    CPC分类号： G06F1/26 ,  G06F1/3203 ,  H03K17/223

    摘要： Conventional bias circuits exhibit a number of limitations, including the time required to power-up a bias circuit following a low-power state. Large current surges in the supply network induce ringing, further complicating a power-up process. Example embodiments reduce power-up time and minimize current surges in the supply by selectively charging and discharging capacitance to the circuit during power-up and power-down of the bias circuit.

    摘要翻译： 常规偏置电路表现出许多限制，包括在低功率状态之后上电偏置电路所需的时间。 供电网络中的大电流浪涌引起振铃，进一步使上电过程复杂化。 示例性实施例通过在偏置电路的加电和掉电期间选择性地对电路充电和放电电容来减小上电时间并最小化电源中的电流浪涌。

    Memory controller with multi-modal reference pad
    6.
    发明授权
    Memory controller with multi-modal reference pad 有权
    内存控制器，具有多模参考焊盘

    公开(公告)号：US08068357B2

    公开(公告)日：2011-11-29

    申请号：US12204728

    申请日：2008-09-04

    申请人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

    发明人： Frederick Ware ,  John Wilson ,  John C. Eble, III ,  Jade M. Kizer ,  Lei Luo ,  John W. Poulton ,  Ian Shaeffer

    IPC分类号： G11C5/06

    CPC分类号： G11C5/063 ,  G11C5/147

    摘要： A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.

    摘要翻译： 存储器控制器以两种模式操作以支持不同类型的存储器件。 在第一模式中，存储器控制器将具有多个信号束中的每一个的专用参考电压分配给相应的多个存储器件。 参考电压使用可替换地用于例如电极的焊盘传送。 定时参考信号处于第二模式，因此针对束特定参考电压的提供不需要增加存储器控制器上的焊盘数量。

    ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION
    7.
    发明申请
    ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION 有权
    多线通信期间的错误检测和偏移消除

    公开(公告)号：US20110051854A1

    公开(公告)日：2011-03-03

    申请号：US12920806

    申请日：2009-02-19

    申请人： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick Ware ,  Jared L. Zerbe

    发明人： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick Ware ,  Jared L. Zerbe

    IPC分类号： H04L27/06

    CPC分类号： H03M13/47 ,  H04L25/4919

    摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols, and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

    摘要翻译： 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 另外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡，以及M个符号集合中的第二值的多个实例，以及如果不平衡 被检测到，它确定了错误条件。

    Error detection and offset cancellation during multi-wire communication
    8.
    发明授权
    Error detection and offset cancellation during multi-wire communication 有权
    多线通讯期间的错误检测和偏移消除

    公开(公告)号：US08462891B2

    公开(公告)日：2013-06-11

    申请号：US12920806

    申请日：2009-02-19

    申请人： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick Ware ,  Jared L. Zerbe

    发明人： Jade M. Kizer ,  John Wilson ,  Lei Luo ,  Frederick Ware ,  Jared L. Zerbe

    IPC分类号： H04L27/06

    CPC分类号： H03M13/47 ,  H04L25/4919

    摘要： Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decoder, coupled to the M input nodes, that determines the codeword in a code space based on the set of M symbols and that decodes the codeword to a corresponding set of N decoded symbols. Additionally, the receive circuit may include a detector that detects an imbalance in a number of instances of a first value in the set of M symbols and a number of instances of a second value in the set of M symbols, and, if an imbalance is detected, that asserts an error condition.

    摘要翻译： 描述电路的实施例。 在该电路中，接收电路包括M个输入节点，该输入节点在时间间隔期间在M个链路上接收一组M个符号，其中该M个符号集合与码字相关联。 此外，接收电路包括耦合到M个输入节点的解码器，其基于该M个符号集来确定码空间中的码字，并且将码字解码为相应的一组N个解码符号。 此外，接收电路可以包括检测器，其检测M个符号集合中的第一值的多个实例中的不平衡以及M个符号集合中的第二值的实例的数量，并且如果不平衡是 检测到，这会导致错误条件。

    Utilizing masked data bits during accesses to a memory
    9.
    发明授权
    Utilizing masked data bits during accesses to a memory 有权
    在访问存储器期间利用屏蔽的数据位

    公开(公告)号：US08581920B2

    公开(公告)日：2013-11-12

    申请号：US12210104

    申请日：2008-09-12

    申请人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

    发明人： Lei Luo ,  Frederick A. Ware ,  John Wilson ,  Jade M. Kizer

    IPC分类号： G09G5/37 ,  G06T1/60

    CPC分类号： G06F9/30018 ,  G09G5/363 ,  G09G5/393 ,  G09G2330/021 ,  G09G2330/06

    摘要： Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.

    摘要翻译： 描述在访问存储器期间使用未使用的被屏蔽的数据位的装置的实施例。 该装置包括选择电路，其选择在访问存储器期间在数据线上驱动的数据位。 该选择电路包括接收数据屏蔽信号的控制输入，该数据屏蔽信号指示在访问存储器期间是否要屏蔽一组数据位。 在访问存储器期间，当数据屏蔽信号未被置位时，选择电路选择要驱动的一组数据位，或者当数据屏蔽信号被断言时要选择要驱动的一组值。

    ASYMMETRIC COMMUNICATION ON SHARED LINKS
    10.
    发明申请
    ASYMMETRIC COMMUNICATION ON SHARED LINKS 有权
    共享链路上的不对称通信

    公开(公告)号：US20100309964A1

    公开(公告)日：2010-12-09

    申请号：US12809000

    申请日：2008-12-19

    申请人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    发明人： Kyung Suk Oh ,  John Wilson ,  Frederick Ware ,  WooPoung Kim ,  Jade M. Kizer ,  Brian S. Leibowitz ,  Lei Luo ,  John Cronan Eble

    IPC分类号： H04B1/38

    CPC分类号： G06F13/4243 ,  H04L25/4906 ,  Y02D10/14 ,  Y02D10/151

    摘要： Embodiments of a system that communicates bidirectional data between two devices via shared links is described. In this system, data is transmitted on the shared links by one of the devices using single-ended drivers, and corresponding symbols are received on the shared links by the other device using differential comparison circuits. The data may be encoded as a series of parallel codewords prior to transmission. Each shared link may communicate a respective symbol in each codeword, which can have one of two possible logical values (e.g., a logic 0 or a logic 1). The corresponding symbols received by the other device may comprise a parallel symbol set, and each of the differential comparison circuits may compare symbols received on pairs of the shared links. A decoder in the other device may decode a respective parallel symbol set from the outputs of the differential comparison circuits to recover the encoded data.

    摘要翻译： 描述通过共享链路在两个设备之间传送双向数据的系统的实施例。 在该系统中，使用单端驱动器的设备之一在共享链路上发送数据，并且使用差分比较电路由另一设备在共享链路上接收对应的符号。 数据可以在传输之前被编码为一系列并行码字。 每个共享链路可以在可以具有两个可能的逻辑值中的一个（例如，逻辑0或逻辑1）的每个码字中传送相应的符号。 由另一设备接收的对应符号可以包括并行符号集合，并且每个差分比较电路可以比较在共享链路对上接收到的符号。 另一设备中的解码器可以从差分比较电路的输出解码相应的并行符号集合，以恢复编码数据。