发明授权
- 专利标题： Wafer planarity control between pattern levels
- 专利标题（中）： 晶片间平面度控制
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申请号： US12757665申请日： 2010-04-09
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公开(公告)号： US08216945B2公开(公告)日： 2012-07-10
- 发明人: Steven L. Prins , Brian K. Kirkpatrick , Amitabh Jain
- 申请人： Steven L. Prins , Brian K. Kirkpatrick , Amitabh Jain
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Jacqueline J. Garner; Wade J. Brady, III; Frederick J. Telecky, Jr.
- 主分类号： H01L21/311
- IPC分类号： H01L21/311 ; H01L21/469 ; H01L21/31
摘要：
A method for controlling the flatness of a wafer between lithography pattern levels. A first lithography step is performed on a topside semiconductor surface of the wafer. Reference curvature information is obtained for the wafer. The reference curvature is other than planar. At least one process step is performed that results in a changed curvature relative to the reference curvature. The changed curvature information is obtained for the wafer. Stress on a bottomside surface of the wafer is modified that reduces a difference between the changed curvature and the reference curvature. A second lithography step is performed on the topside semiconductor surface while the modified stress distribution is present.
公开/授权文献
- US20100261353A1 WAFER PLANARITY CONTROL BETWEEN PATTERN LEVELS 公开/授权日：2010-10-14
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