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    MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS
    1.
    发明申请
    MOS TRANSISTORS INCLUDING SiON GATE DIELECTRIC WITH ENHANCED NITROGEN CONCENTRATION AT ITS SIDEWALLS 有权
    包括SiON GATE介电的MOS晶体管，在其边界具有增强的氮浓度

    公开(公告)号：US20120032280A1

    公开(公告)日：2012-02-09

    申请号：US12850097

    申请日：2010-08-04

    申请人： Brian K. Kirkpatrick ,  James Joseph Chambers

    发明人： Brian K. Kirkpatrick ,  James Joseph Chambers

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/518 ,  H01L21/28044 ,  H01L21/28202 ,  H01L29/78

    摘要： A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ≧ the N concentration in a bulk of the annealed N-enhanced SiON gate layer −2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.

    摘要翻译： 形成具有至少一个MOS器件的集成电路（IC）的方法包括在硅表面上形成SiON栅介质层。 在SiON栅极层上沉积栅电极层，然后构图形成栅叠层。 通过图案化揭示了暴露的栅极电介质侧壁。 在暴露的SiON侧壁上形成补充的氧化硅层，然后氮化。 氮化后，后氮化退火（PNA）形成包括N增强SiON侧壁的退火的N增强SiON栅极电介质层，其中沿着恒定厚度的线，N增强SiON侧壁处的N浓度为≥N 大部分退火的N增强SiON栅极层为-2原子％。 形成栅极堆叠的相对侧上的源极和漏极区域以限定栅极叠层下方的沟道区域。

    Nitride removal while protecting semiconductor surfaces for forming shallow junctions
    3.
    发明授权
    Nitride removal while protecting semiconductor surfaces for forming shallow junctions 有权
    氮化物去除同时保护半导体表面以形成浅结

    公开(公告)号：US08043921B2

    公开(公告)日：2011-10-25

    申请号：US12731913

    申请日：2010-03-25

    申请人： Brian K. Kirkpatrick ,  Deborah J. Riley

    发明人： Brian K. Kirkpatrick ,  Deborah J. Riley

    IPC分类号： H01L21/336

    CPC分类号： H01L21/2652 ,  H01L29/6653 ,  H01L29/6656

    摘要： A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.

    摘要翻译： 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成，其一起限定轻掺杂漏极（LDD）区域或源极/漏极（S / D）区域。 侧壁间隔物，LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除，其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层，或者当LDD或S / D区域包括 暴露的氮化硅层，在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。

    Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics
    4.
    发明授权
    Cross-contamination control for processing of circuits comprising MOS devices that include metal comprising high-K dielectrics 有权
    用于处理包括包含高K电介质的金属的MOS器件的电路的交叉污染控制

    公开(公告)号：US07968443B2

    公开(公告)日：2011-06-28

    申请号：US12344360

    申请日：2008-12-26

    申请人： Brian K. Kirkpatrick ,  James J. Chambers

    发明人： Brian K. Kirkpatrick ,  James J. Chambers

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/51 ,  H01L21/28247 ,  H01L21/31111 ,  H01L29/495

    摘要： A cross method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface, wherein the bevel semiconductor surface and backside semiconductor surface include silicon or germanium. A metal including high-k gate dielectric layer is formed on at least the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and backside semiconductor surface. The high-k dielectric material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed while protecting the high-k dielectric layer on the topside semiconductor surface. The selective removing includes a first oxidizing treatment, and a fluoride including wet etch follows the first oxidizing treatment. The fabrication of the IC is completed including forming at least one metal gate layer on the high-k gate dielectric layer after the selectively removing step.

    摘要翻译： 制造CMOS集成电路（IC）的交叉方法包括提供具有顶侧半导体表面，斜面半导体表面和背面半导体表面的半导体晶片，其中斜面半导体表面和背面半导体表面包括硅或锗。 至少在顶侧半导体表面和斜面半导体表面和背面半导体表面的至少一部分上形成包括高k栅极电介质层的金属。 选择性地去除斜面半导体表面和背面半导体表面上的高k介电材料，同时保护顶侧半导体表面上的高k电介质层。 选择性除去包括第一氧化处理，并且包含湿蚀刻的氟化物遵循第一氧化处理。 完成IC的制造，包括在选择性除去步骤之后在高k栅极电介质层上形成至少一个金属栅极层。

    CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS
    5.
    发明申请
    CURVATURE REDUCTION FOR SEMICONDUCTOR WAFERS 有权
    半导体波长的减少曲线

    公开(公告)号：US20100261298A1

    公开(公告)日：2010-10-14

    申请号：US12757704

    申请日：2010-04-09

    申请人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

    发明人： Brian K. Kirkpatrick ,  Steven L. Prins ,  Amitabh Jain

    IPC分类号： H01L21/26 ,  H01L21/66

    CPC分类号： H01L21/26506 ,  H01L21/02532 ,  H01L21/02658 ,  H01L21/02667 ,  H01L22/12 ,  H01L22/20

    摘要： A method for reducing curvature of a wafer having a semiconductor surface. One or more process steps are identified at which wafers exhibit the largest curvature, and/or wafer curvature that may reduce die yield. A crystal damaging process converts at least a portion of the semiconductor surface into at least one amorphous surface region After or contemporaneously with the crystal damaging, the amorphous surface region is recrystallized by recrystallization annealing that anneals the wafer for a time ≦5 seconds at a temperature sufficient for recrystallization of the amorphous surface region. A subsequent photolithography step is facilitated due to the reduction in average wafer curvature provided by the recrystallization.

    摘要翻译： 一种用于减小具有半导体表面的晶片的曲率的方法。 识别一个或多个工艺步骤，在该处理步骤中，晶片呈现最大的曲率，和/或晶片曲率，其可以降低模具的产量。 晶体损伤过程将半导体表面的至少一部分转化成至少一个非晶表面区域在晶体损坏之后或同时具有晶体损伤的情况下，非晶表面区域通过重结晶退火重结晶，使晶片退火一段时间， 足以使非晶表面区域再结晶的温度。 由于再结晶提供的平均晶片曲率的减小，随后的光刻步骤变得容易。

    Gate dielectric first replacement gate processes and integrated circuits therefrom
    10.
    发明授权
    Gate dielectric first replacement gate processes and integrated circuits therefrom 有权
    栅介质第一替代栅极工艺及其集成电路

    公开(公告)号：US07838356B2

    公开(公告)日：2010-11-23

    申请号：US12347197

    申请日：2008-12-31

    申请人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    发明人： Brian K. Kirkpatrick ,  Freidoon Mehrad ,  Shaofeng Yu

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    摘要： A method for fabricating a CMOS integrated circuit (IC) and ICs therefrom includes the steps of providing a substrate having a semiconductor surface, wherein the semiconductor surface has PMOS regions for PMOS devices and NMOS regions for NMOS devices. A gate dielectric layer is formed on the PMOS regions and NMOS regions. An original gate electrode layer is formed on the gate dielectric layer. A gate masking layer is applied on the gate electrode layer. Etching is used to pattern the original gate electrode layer to simultaneously form original gate electrodes for the PMOS devices and NMOS devices. Source and drain regions are formed for the PMOS devices and NMOS devices. The original gate electrodes are removed for at least one of the PMOS devices and NMOS devices to form trenches using an etch process, such as a hydroxide-based solution, wherein at least a portion and generally substantially all of the gate dielectric layer is preserved. A metal comprising replacement gates is formed in the trenches, and fabrication of the IC is completed.

    摘要翻译： 一种用于制造CMOS集成电路（IC）及其IC的方法包括提供具有半导体表面的衬底的步骤，其中半导体表面具有用于PMOS器件的PMOS区域和用于NMOS器件的NMOS区域。 栅极电介质层形成在PMOS区域和NMOS区域上。 在栅极电介质层上形成原始栅电极层。 栅极掩模层被施加在栅极电极层上。 蚀刻用于对原始栅极电极层进行图案化以同时形成用于PMOS器件和NMOS器件的原始栅电极。 为PMOS器件和NMOS器件形成源极和漏极区域。 为了至少一个PMOS器件和NMOS器件去除原始栅电极，以使用诸如基于氢氧化物的溶液的蚀刻工艺形成沟槽，其中保留了栅极电介质层的至少一部分和基本上全部的栅极电介质层。 在沟槽中形成包括置换栅极的金属，并且完成IC的制造。