发明授权
US08278752B2 Microelectronic package and method for a compression-based mid-level interconnect
有权
用于基于压缩的中级互连的微电子封装和方法
- 专利标题： Microelectronic package and method for a compression-based mid-level interconnect
- 专利标题（中）： 用于基于压缩的中级互连的微电子封装和方法
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申请号： US12646854申请日： 2009-12-23
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公开(公告)号： US08278752B2公开(公告)日： 2012-10-02
- 发明人: Brent M. Roberts , Mihir K. Roy , Sriram Srinivasan , Sridhar Narasimhan
- 申请人： Brent M. Roberts , Mihir K. Roy , Sriram Srinivasan , Sridhar Narasimhan
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： H01L23/34
- IPC分类号： H01L23/34 ; H01L23/48
摘要：
A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.
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