Microelectronic package and method for a compression-based mid-level interconnect
    2.
    发明授权
    Microelectronic package and method for a compression-based mid-level interconnect 有权
    用于基于压缩的中级互连的微电子封装和方法

    公开(公告)号:US08278752B2

    公开(公告)日:2012-10-02

    申请号:US12646854

    申请日:2009-12-23

    IPC分类号: H01L23/34 H01L23/48

    摘要: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

    摘要翻译: 微电子封装包括具有第一表面区域(125)的第一衬底(120)和具有第二表面区域(135)的第二衬底(130)。 第一衬底包括在第一表面处具有第一间距(127)的第一组互连(126)和在第二表面(222)处具有第二间距(129)的第二组互连(128)。 第二衬底使用第二组互连件耦合到第一衬底,并且包括具有第三间距(237)的第三组互连(236)和用微孔(240)彼此连接的内部导电层(233,234)。 第一间距小于第二间距,第二间距小于第三间距,第一表面积小于第二表面积。

    MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT
    4.
    发明申请
    MICROELECTRONIC PACKAGE AND METHOD FOR A COMPRESSION-BASED MID-LEVEL INTERCONNECT 有权
    用于基于压缩的中间级互连的微电子封装和方法

    公开(公告)号:US20110147913A1

    公开(公告)日:2011-06-23

    申请号:US12646854

    申请日:2009-12-23

    IPC分类号: H01L23/522 H01L21/50

    摘要: A microelectronic package includes first substrate (120) having first surface area (125) and second substrate (130) having second surface area (135). The first substrate includes first set of interconnects (126) having first pitch (127) at first surface (121) and second set of interconnects (128) having second pitch (129) at second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes third set of interconnects (236) having third pitch (237) and internal electrically conductive layers (233,234) connected to each other with microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

    摘要翻译: 微电子封装包括具有第一表面区域(125)的第一衬底(120)和具有第二表面区域(135)的第二衬底(130)。 第一衬底包括在第一表面处具有第一间距(127)的第一组互连(126)和在第二表面(222)处具有第二间距(129)的第二组互连(128)。 第二衬底使用第二组互连件耦合到第一衬底,并且包括具有第三间距(237)的第三组互连(236)和用微孔(240)彼此连接的内部导电层(233,234)。 第一间距小于第二间距,第二间距小于第三间距,第一表面积小于第二表面积。