发明授权
US08344921B2 Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
有权
具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法
- 专利标题： Sigma-delta modulator with SAR ADC and truncater having order lower than order of integrator and related sigma-delta modulation method
- 专利标题（中）： 具有SAR ADC和截断器的Σ-Δ调制器具有低于积分器的阶数和相关的Σ-Δ调制方法
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申请号： US13072797申请日： 2011-03-28
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公开(公告)号： US08344921B2公开(公告)日： 2013-01-01
- 发明人: Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
- 申请人： Yu-Hsin Lin , Hung-Chieh Tsai , Sheng-Jui Huang
- 申请人地址： TW Science-Based Industrial Park, Hsin-Chu
- 专利权人： Mediatek Inc.
- 当前专利权人： Mediatek Inc.
- 当前专利权人地址： TW Science-Based Industrial Park, Hsin-Chu
- 代理商 Winston Hsu; Scott Margo
- 主分类号： H03M3/00
- IPC分类号： H03M3/00
摘要：
A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information, wherein an order of the truncater is lower than an order of the integration.
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