发明授权
US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices
有权
用于硬化SOI CMOS器件中的锁存器的装置和方法
- 专利标题: Apparatus and method for hardening latches in SOI CMOS devices
- 专利标题(中): 用于硬化SOI CMOS器件中的锁存器的装置和方法
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申请号: US12987106申请日: 2011-01-08
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公开(公告)号: US08354858B2公开(公告)日: 2013-01-15
- 发明人: Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
- 申请人: Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Carey, Rodriguez, Greenberg & O'Keefe
- 代理商 Steven M. Greenberg, Esq.
- 主分类号: G01R31/26
- IPC分类号: G01R31/26
摘要:
A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.