Invention Grant
- Patent Title: Manufacturing method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US12839668Application Date: 2010-07-20
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Publication No.: US08357933B2Publication Date: 2013-01-22
- Inventor: Akio Hasebe , Hideyuki Matsumoto , Shingo Yorisaki , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka , Naoki Okamoto
- Applicant: Akio Hasebe , Hideyuki Matsumoto , Shingo Yorisaki , Yasuhiro Motoyama , Masayoshi Okamoto , Yasunori Narizuka , Naoki Okamoto
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Mattingly & Malur, P.C.
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.
Public/Granted literature
- US20100277192A1 MANUFACTORING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2010-11-04
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