发明授权
- 专利标题: Mode latching buffer circuit
- 专利标题(中): 模式锁存缓冲电路
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申请号: US13031176申请日: 2011-02-18
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公开(公告)号: US08362803B2公开(公告)日: 2013-01-29
- 发明人: Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
- 申请人: Peter J. Nicholas , John Christopher Kriz , Dipankar Bhattacharya , James John Bradley
- 申请人地址: US CA Milpitas
- 专利权人: LSI Corporation
- 当前专利权人: LSI Corporation
- 当前专利权人地址: US CA Milpitas
- 代理机构: Otterstedt, Ellenbogen & Kammer, LLP
- 主分类号: H03K19/0175
- IPC分类号: H03K19/0175
摘要:
A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.
公开/授权文献
- US20120212256A1 Mode Latching Buffer Circuit 公开/授权日:2012-08-23