Mode latching buffer circuit
    1.
    发明授权
    Mode latching buffer circuit 有权
    模式锁存缓冲电路

    公开(公告)号:US08362803B2

    公开(公告)日:2013-01-29

    申请号:US13031176

    申请日:2011-02-18

    IPC分类号: H03K19/0175

    摘要: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

    摘要翻译: 电压转换器电路包括适于接收参考第一电压源的输入信号的输入级,适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路,以及 电压钳耦合在输入级和第一锁存电路之间。 电压钳可用于将输入级两端的最大电压设定到规定的电平。 电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。 第二锁存电路以反馈配置连接到第一输出端。 第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数,而与第一电压源的状态无关。

    Mode Latching Buffer Circuit
    2.
    发明申请
    Mode Latching Buffer Circuit 有权
    模式锁存缓冲电路

    公开(公告)号:US20120212256A1

    公开(公告)日:2012-08-23

    申请号:US13031176

    申请日:2011-02-18

    IPC分类号: H03K19/0175 H03K5/08

    摘要: A voltage translator circuit includes an input stage adapted for receiving an input signal referenced to a first voltage supply, a first latch circuit adapted for connection with a second voltage supply and operative to at least temporarily store a logic state of the input signal, and a voltage clamp coupled between the input stage and the first latch circuit. The voltage clamp is operative to set a maximum voltage across the input stage to a prescribed level. The voltage translator circuit generates a first output signal at a first output formed at a junction between the first latch circuit and the voltage clamp. A second latch circuit is connected to the first output in a feedback configuration. The second latch circuit is operative to retain a logical state of the first output signal as a function of at least a first control signal supplied to the second latch circuit regardless of a state of the first voltage supply.

    摘要翻译: 电压转换器电路包括适于接收参考第一电压源的输入信号的输入级,适于与第二电压源连接并可操作以至少临时存储输入信号的逻辑状态的第一锁存电路,以及 电压钳耦合在输入级和第一锁存电路之间。 电压钳可用于将输入级两端的最大电压设定到规定的电平。 电压转换器电路在形成在第一锁存电路和电压钳之间的结处的第一输出处产生第一输出信号。 第二锁存电路以反馈配置连接到第一输出端。 第二锁存电路用于将第一输出信号的逻辑状态保持为至少提供给第二锁存电路的第一控制信号的函数,而与第一电压源的状态无关。