发明授权
- 专利标题： Integrated high-K/metal gate in CMOS process flow
- 专利标题（中）： CMOS工艺流程中集成的高K /金属栅极
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申请号： US13186572申请日： 2011-07-20
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公开(公告)号： US08383502B2公开(公告)日： 2013-02-26
- 发明人: Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
- 申请人： Ryan Chia-Jen Chen , Yih-Ann Lin , Jr Jung Lin , Yi-Shien Mor , Chien-Hao Chen , Kuo-Tai Huang , Yi-Hsing Chen
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205 ; H01L21/4763
摘要：
A method of fabricating a semiconductor device includes providing a semiconductor substrate having a first active region and a second active region, forming a first metal layer over a high-k dielectric layer, removing at least a portion of the first metal layer in the second active region, forming a second metal layer on first metal layer in the first active region and over the high-k dielectric layer in the second active region, and thereafter, forming a silicon layer over the second metal layer. The method further includes removing the silicon layer from the first gate stack thereby forming a first trench and from the second gate stack thereby forming a second trench, and forming a third metal layer over the second metal layer in the first trench and over the second metal layer in the second trench.
公开/授权文献
- US20110275212A1 Integrated High-K/Metal Gate in CMOS Process Flow 公开/授权日：2011-11-10
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