Invention Grant
US08384425B2 Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate 有权
具有埋置在绝缘体上半导体衬底的绝缘膜下方的后控制栅极的晶体管阵列

  • Patent Title: Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate
  • Patent Title (中): 具有埋置在绝缘体上半导体衬底的绝缘膜下方的后控制栅极的晶体管阵列
  • Application No.: US12961293
    Application Date: 2010-12-06
  • Publication No.: US08384425B2
    Publication Date: 2013-02-26
  • Inventor: Carlos MazureRichard Ferrant
  • Applicant: Carlos MazureRichard Ferrant
  • Applicant Address: FR Bernin
  • Assignee: Soitec
  • Current Assignee: Soitec
  • Current Assignee Address: FR Bernin
  • Agency: Winston & Strawn LLP
  • Priority: FR0958747 20091208
  • Main IPC: H03K19/173
  • IPC: H03K19/173 H03K3/01 H01L27/12
Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate
Abstract:
This invention provides a semiconductor device structure formed on a conventional semiconductor-on-insulator (SeOI) substrate and including an array of patterns, each pattern being formed by at least one field-effect transistor, each FET transistor having, in the thin film, a source region, a drain region, a channel region, and a front control gate region formed above the channel region. The provided device further includes at least one FET transistor having a pattern including a back control gate region formed in the base substrate beneath the channel region, the back gate region being capable of being biased in order to shift the threshold voltage of the transistor to simulate a modification in the channel width of the transistor or to force the transistor to remain off or on whatever the voltage applied on its front control gate. This invention also provides methods of operating such semiconductor device structures.
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