发明授权
- 专利标题: Semiconductor integrated circuit device and method for evaluating an eye-opening margin
- 专利标题(中): 半导体集成电路装置及评估开眼余量的方法
-
申请号: US12367067申请日: 2009-02-06
-
公开(公告)号: US08443243B2公开(公告)日: 2013-05-14
- 发明人: Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , Kazuhisa Suzuki
- 申请人: Akira Matsumoto , Daisuke Hamano , Atsuhiro Hayashi , Kazuhisa Suzuki
- 申请人地址: JP Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JP Tokyo
- 代理机构: Mattingly & Malur, PC
- 优先权: JP2008-055696 20080306
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.
公开/授权文献
信息查询