公开(公告)号：US08443243B2

公开(公告)日：2013-05-14

申请号：US12367067

申请日：2009-02-06

申请人： Akira Matsumoto ,  Daisuke Hamano ,  Atsuhiro Hayashi ,  Kazuhisa Suzuki

发明人： Akira Matsumoto ,  Daisuke Hamano ,  Atsuhiro Hayashi ,  Kazuhisa Suzuki

IPC分类号： G06F11/00

CPC分类号： H03L7/08 ,  H04L1/205 ,  H04L7/0008 ,  H04L7/0331 ,  H04L7/043

摘要： An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.

摘要翻译： 一种用于高速串行数据接收电路的开眼边缘测量方法，其使用涉及在不固定时钟相位的情况下操作时钟数据恢复电路的眼睛开度边缘测量电路。 在该方法中，也可以通过向相位信息给出偏移脉冲信号来添加抖动分量，来对接收到的数据进行误差加速度测试。 该方法使用包括用于接收串行数据的串行器/解串行器电路（SerDes）和用于接收伴随时钟信号的参考串行器/解串行器电路（Ref_SerDes）的半导体集成电路器件。 SerDes电路通过恢复时钟将接收的串行数据转换成并行数据，恢复时钟的相位由Ref_SerDes电路生成的相位控制信号P_CS进行控制。 来自脉冲形成电路的偏移脉冲信号Offset_Pulse被施加到相位控制信号P_CS以进行开眼余量测量。

公开(公告)号：US06538293B2

公开(公告)日：2003-03-25

申请号：US10142062

申请日：2002-05-10

申请人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

发明人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

IPC分类号： H01L31119

CPC分类号： H01L27/0629 ,  Y10S438/981

摘要： A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

公开(公告)号：US20110056833A1

公开(公告)日：2011-03-10

申请号：US12672409

申请日：2008-07-08

申请人： Kazuhisa Suzuki ,  Mika Suzuki ,  Yukiko Minegishi

发明人： Kazuhisa Suzuki ,  Mika Suzuki ,  Yukiko Minegishi

IPC分类号： G01N27/447 ,  B29C35/08

CPC分类号： G01N27/44747

摘要： This invention relates to a precast gel for electrophoresis comprising a support filled with an aqueous gel prepared by polymerizing an aqueous solution comprising a radically polymerizable monomer, a crosslinkable monomer, a buffer, a redox initiator comprising an oxidizer/reducer, and a photo sensitizer and having a pH level of 6.0 to 7.5 via light application. The slab gel for electrophoresis of the present invention can produce a precast gel for electrophoresis within a shorter period of time and in an easier manner than is possible with conventional techniques. Accordingly, the present invention enables production of a high-quality precast gel for electrophoresis in terms of productivity, cost, and quality, and the industrial applicability thereof is remarkable.

摘要翻译： 本发明涉及一种用于电泳的预制凝胶，其包括填充有水性凝胶的载体，其通过聚合包含可自由基聚合的单体，可交联单体，缓冲剂，包含氧化剂/还原剂的氧化还原引发剂和光敏剂的水溶液制备， 通过光照施用pH值为6.0至7.5。 本发明的电泳用板状凝胶可以在较短的时间内以比常规技术更容易的方式制造电泳用预制凝胶。 因此，本发明能够在生产率，成本和质量方面制造用于电泳的高质量预制凝胶，其工业应用性显着。

公开(公告)号：US06492203B1

公开(公告)日：2002-12-10

申请号：US09680369

申请日：2000-10-05

申请人： Yoshiaki Wakashima ,  Naoki Fukutomi ,  Kazuhisa Suzuki ,  Toshio Yamazaki ,  Tsutomu Kitakatsu ,  Susumu Naoyuki ,  Akinari Kida

发明人： Yoshiaki Wakashima ,  Naoki Fukutomi ,  Kazuhisa Suzuki ,  Toshio Yamazaki ,  Tsutomu Kitakatsu ,  Susumu Naoyuki ,  Akinari Kida

IPC分类号： H01L2144

CPC分类号： H01L24/85 ,  H01L21/4803 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L29/0657 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48624 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15157 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/78 ,  H01L2924/00

摘要： A semiconductor device fabrication process comprising an encapsulation step of carrying out encapsulation by vacuum pressure differential printing by the use of a liquid resin encapsulant containing a solvent in an amount of from 5% by weight to 50% by weight, and preferably from 25% by weight to 50% by weight. The encapsulation step comprises: printing the liquid resin encapsulant by vacuum pressure differential printing in such a way that; the encapsulant covers at least an internal connecting terminal provided on a substrate, a semiconductor chip, and a wire interconnecting the internal connecting terminal and the semiconductor chip; and that the thickness of the encapsulant lying above the wire at the highest position of the wire comes to be at least 0.8 times the thickness of the encapsulant lying beneath the wire at the same position; and curing or drying the encapsulant.

摘要翻译： 一种半导体器件制造方法，包括通过真空压差印刷进行封装的封装步骤，所述封装步骤通过使用含有溶剂的液体树脂密封剂，其量为5重量％至50重量％，优选25重量％ 重量至50％重量。 封装步骤包括：通过真空压差印刷印刷液态树脂密封剂， 密封剂至少覆盖设置在基板上的内部连接端子，半导体芯片和互连内部连接端子和半导体芯片的布线; 并且位于电线最高位置处的线上方的密封剂的厚度至少为位于相同位置下方的密封剂厚度的至少0.8倍; 并固化或干燥密封剂。

公开(公告)号：US06327446B1

公开(公告)日：2001-12-04

申请号：US09525470

申请日：2000-03-15

申请人： Kazuhisa Suzuki

发明人： Kazuhisa Suzuki

IPC分类号： G03G1500

CPC分类号： H04N1/00973 ,  G03G15/5075 ,  G03G2215/00109 ,  H04N1/00344 ,  H04N2201/0022

摘要： A multi-mode image forming apparatus and method have a first mode which can be used by all users and a second mode which is available to authorized users only. The second mode is induced in response to a request from a management apparatus which is connected image forming apparatus. A reception arrangement is arranged to receive updating data sent from the management apparatus in the second mode and to store this data in a memory from which a non-volatile memory of the image forming apparatus can be updated at a later time. This arrangement permits file data to be transferred from the management apparatus to a HDD in the image forming apparatus. During an update, this data can be read out from the HDD to an EEPROM (non-volatile memory) so that even if the updating operation fails, the time for repeating the updating can be minimized.

摘要翻译： 多模式图像形成装置和方法具有可被所有用户使用的第一模式和仅对授权用户可用的第二模式。 响应于来自连接图像形成装置的管理装置的请求而引起第二模式。 接收装置被设置为接收在第二模式中从管理装置发送的更新数据，并将该数据存储在可以在稍后时间更新图像形成装置的非易失性存储器的存储器中。 这种布置允许文件数据从管理装置传送到图像形成装置中的HDD。 在更新期间，该数据可以从HDD读取到EEPROM（非易失性存储器），使得即使更新操作失败，可以最小化重复更新的时间。

公开(公告)号：US5673601A

公开(公告)日：1997-10-07

申请号：US381856

申请日：1995-02-07

申请人： Kikuo Ejima ,  Kenji Nishikawa ,  Kazuya Imamura ,  Kazuhisa Suzuki ,  Shigeki Iwasaki ,  Tatsunori Suwa

发明人： Kikuo Ejima ,  Kenji Nishikawa ,  Kazuya Imamura ,  Kazuhisa Suzuki ,  Shigeki Iwasaki ,  Tatsunori Suwa

IPC分类号： B21D28/34 ,  B21D28/20 ,  B30B15/00 ,  B30B15/02 ,  B30B15/28 ,  B26D5/12

CPC分类号： B21D28/20 ,  B30B15/0076 ,  Y10T83/04 ,  Y10T83/141 ,  Y10T83/152 ,  Y10T83/8858 ,  Y10T83/8864

摘要： A breakthrough buffer for a mechanical press (1) includes at least one buffer body (20) disposed between punch slide (2) and lower press frame (7) to cushion punch plate (3) during breakthrough of punch (4) through a workpiece, a timing regulator (40, 70, 90) connected to each buffer body for regulating timing of buffering during breakthrough, and a control system (60) to provide a command signal to this regulator to minimize noise or vibration occurring during the breakthrough. The control system includes a controller (63) which is responsive to the output of noise sensor (61) or vibration sensor (65) during breakthrough. The buffer body can include fluid driven buffer piston (22) in a buffer cylinder (21), with the buffer piston being associated with a guidepost (5). Alternatively, the buffer body can include piston (82) which contacts the guidepost and which is fluid driven (30, 81) in opposition to spring (83). The timing regulator can include an annular guide (46, 71) which is movable vertically by stepping motor (41) and worm gear drive (42, 44). A locking mechanism (73) can restrain trailing whirl of the guide. Alternatively, the timing regulator can include regulating piston (94) in regulating actuator (93), with fluid pressure on one side being controlled by proportional valve (91) responsive to the command signal, while fluid pressure on the other side is applied to each buffer piston.

摘要翻译： PCT No.PCT / JP93 / 01063 Sec。 371日期：1995年2月7日 102（e）1995年2月7日PCT PCT 1993年7月28日PCT公布。 公开号WO94 / 05488 日期1994年3月17日机械压力机（1）的突破缓冲器包括至少一个设置在冲头滑块（2）和下压框（7）之间的缓冲体（20），以在冲头穿透期间缓冲冲压板（3） 4）通过工件连接到每个缓冲体的定时调节器（40,70,90），用于调节穿透期间的缓冲定时;以及控制系统（60），用于向该调节器提供命令信号以最小化发生的噪声或振动 在突破之中。 控制系统包括在突破期间响应于噪声传感器（61）或振动传感器（65）的输出的控制器（63）。 缓冲体可以包括缓冲气缸（21）中的流体驱动缓冲活塞（22），缓冲活塞与路标（5）相关联。 或者，缓冲体可以包括与路标相接触并与弹簧（83）相对的流体驱动（30,81）的活塞（82）。 定时调节器可以包括环形引导件（46,71），其可通过步进马达（41）和蜗轮传动装置（42,44）垂直移动。 锁定机构（73）可以限制引导件的旋转。 或者，定时调节器可以包括调节致动器（93）中的调节活塞（94），一侧的流体压力响应于指令信号由比例阀（91）控制，而另一侧的流体压力被施加到每个 缓冲活塞。

公开(公告)号：US08706492B2

公开(公告)日：2014-04-22

申请号：US13170284

申请日：2011-06-28

申请人： Kunio Yokoi ,  Kazuhisa Suzuki ,  Masayuki Takami ,  Naoyori Tanzawa

发明人： Kunio Yokoi ,  Kazuhisa Suzuki ,  Masayuki Takami ,  Naoyori Tanzawa

IPC分类号： G10L13/00

CPC分类号： G01C21/3608 ,  G01C21/3629 ,  G10L13/00 ,  G10L15/22 ,  G10L15/30

摘要： A voice recognition terminal executes a local voice recognition process and utilizes an external center voice recognition process. The terminal includes: a voice message synthesizing element for synthesizing at least one of a voice message to be output from a speaker according to the external center voice recognition process and a voice message to be output from the speaker according to the local voice recognition process so as to distinguish between characteristics of the voice message to be output from the speaker according to the external center voice recognition process and characteristics of the voice message to be output from the speaker according to the local voice recognition process; and a voice output element for outputting a synthesized voice message from the speaker.

摘要翻译： 语音识别终端执行本地语音识别处理并利用外部中心语音识别处理。 该终端包括：语音消息合成元件，用于根据外部中心语音识别处理和从语音信号根据本地语音识别处理从扬声器输出的语音消息合成要从扬声器输出的语音消息中的至少一个， 根据本地语音识别过程，根据外部中心语音识别处理和从扬声器输出的语音消息的特征来区分要从扬声器输出的语音消息的特性; 以及用于从扬声器输出合成语音消息的语音输出元件。

公开(公告)号：US07424081B2

公开(公告)日：2008-09-09

申请号：US10863258

申请日：2004-06-09

申请人： Kazuhisa Suzuki

发明人： Kazuhisa Suzuki

IPC分类号： H04L7/00

CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091 ,  H04L7/0337

摘要： An error rate of a bit synchronous circuit is decreased to a large extent by preventing following excessively the jitters included in input data. A phase detect circuit of a bit synchronous circuit includes a majority decision circuit. The majority decision circuit counts UP0 and DN0 signals as a phase comparison result of comparing phases by a UP0 counter and a DN0 counter for a period of time, and its count number is judged by a magnitude relation determination circuit. The magnitude relation determination circuit outputs an UP signal if the UP0 signal is majority, a DN signal if the DN0 signal is majority, and a FIX signal if the UP0 signal is equal to the DN0 signal. Accordingly, since it is possible to prevent following the jitters included in input data, etc., an error rate for bit synchronization can be reduced to a large extent.

摘要翻译： 通过防止过多地包含在输入数据中的抖动，同步电路的错误率在很大程度上降低。 位同步电路的相位检测电路包括多数决定电路。 多数决定电路对UP0和DN0信号进行计数，作为在一段时间内由UP0计数器和DN0计数器进行比较相位的相位比较结果，并且其数量由大小关系确定电路判断。 如果UP0信号为多数，则大小关系确定电路输出UP信号，如果DN0信号为多数，则输出DN信号，如果UP0信号等于DN0信号，则输出FIX信号。 因此，由于可以防止跟随包含在输入数据等中的抖动，所以可以在很大程度上减少位同步的错误率。

公开(公告)号：US20050008111A1

公开(公告)日：2005-01-13

申请号：US10863258

申请日：2004-06-09

申请人： Kazuhisa Suzuki

发明人： Kazuhisa Suzuki

IPC分类号： H04L7/02 ,  H03L7/07 ,  H03L7/081 ,  H03L7/089 ,  H03L7/091 ,  H03L7/18 ,  H04L7/033 ,  H01L23/62 ,  H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03L7/18 ,  H03L7/07 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/091 ,  H04L7/0337

摘要： An error rate of a bit synchronous circuit is decreased to a large extent by preventing following excessively the jitters included in input data. A phase detect circuit of a bit synchronous circuit includes a majority decision circuit. The majority decision circuit counts UP0 and DN0 signals as a phase comparison result of comparing phases by a UP0 counter and a DN0 counter for a period of time, and its count number is judged by a magnitude relation determination circuit. The magnitude relation determination circuit outputs an UP signal if the UP0 signal is majority, a DN signal if the DN0 signal is majority, and a FIX signal if the UP0 signal is equal to the DN0 signal. Accordingly, since it is possible to prevent following the jitters included in input data, etc., an error rate for bit synchronization can be reduced to a large extent.

摘要翻译： 通过防止过多地包含在输入数据中的抖动，同步电路的错误率在很大程度上降低。 位同步电路的相位检测电路包括多数决定电路。 多数决定电路对UP0和DN0信号进行计数，作为在一段时间内由UP0计数器和DN0计数器进行比较相位的相位比较结果，并且其数量由大小关系确定电路判断。 如果UP0信号为多数，则大小关系确定电路输出UP信号，如果DN0信号为多数，则输出DN信号，如果UP0信号等于DN0信号，则输出FIX信号。 因此，由于可以防止跟随包含在输入数据等中的抖动，所以可以在很大程度上减少位同步的错误率。

公开(公告)号：US06433398B1

公开(公告)日：2002-08-13

申请号：US09661372

申请日：2000-09-13

申请人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

发明人： Kazuhisa Suzuki ,  Toshiro Takahashi ,  Yasunobu Yanagisawa ,  Yusuke Nonaka

IPC分类号： H01L2972

CPC分类号： H01L27/0629 ,  Y10S438/981

摘要： A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power-supply voltage.

摘要翻译： 通过利用比构成CMOS栅极阵列的逻辑部分的MISFET更厚的栅极氧化膜9B形成具有小的漏电流的电容元件C1，而不增加制造CMOS门阵列的步骤数。 电容元件C1是栅电极10E。 栅电极10E的一部分由多晶硅膜制成。 多晶硅膜掺杂有n型杂质，使得即使在低电源电压下，电容元件也可以可靠地工作。