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1.发明授权Semiconductor integrated circuit device and method for evaluating an eye-opening margin 有权半导体集成电路装置及评估开眼余量的方法公开(公告)号：US08443243B2
公开(公告)日：2013-05-14
申请号：US12367067
申请日：2009-02-06
IPC分类号： G06F11/00
CPC分类号： H03L7/08 , H04L1/205 , H04L7/0008 , H04L7/0331 , H04L7/043
摘要： An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.
摘要翻译： 一种用于高速串行数据接收电路的开眼边缘测量方法，其使用涉及在不固定时钟相位的情况下操作时钟数据恢复电路的眼睛开度边缘测量电路。 在该方法中，也可以通过向相位信息给出偏移脉冲信号来添加抖动分量，来对接收到的数据进行误差加速度测试。 该方法使用包括用于接收串行数据的串行器/解串行器电路（SerDes）和用于接收伴随时钟信号的参考串行器/解串行器电路（Ref_SerDes）的半导体集成电路器件。 SerDes电路通过恢复时钟将接收的串行数据转换成并行数据，恢复时钟的相位由Ref_SerDes电路生成的相位控制信号P_CS进行控制。 来自脉冲形成电路的偏移脉冲信号Offset_Pulse被施加到相位控制信号P_CS以进行开眼余量测量。
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2.发明申请SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR EVALUATING AN EYE-OPENING MARGIN 有权半导体集成电路装置和评估眼睛开放标志的方法公开(公告)号：US20090224809A1
公开(公告)日：2009-09-10
申请号：US12367067
申请日：2009-02-06
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , H04L1/205 , H04L7/0008 , H04L7/0331 , H04L7/043
摘要： An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.
摘要翻译： 一种用于高速串行数据接收电路的开眼边缘测量方法，其使用涉及在不固定时钟相位的情况下操作时钟数据恢复电路的眼睛开度边缘测量电路。 在该方法中，也可以通过向相位信息给出偏移脉冲信号来添加抖动分量，来对接收到的数据进行误差加速度测试。 该方法使用包括用于接收串行数据的串行器/解串行器电路（SerDes）和用于接收伴随时钟信号的参考串行器/解串行器电路（Ref_SerDes）的半导体集成电路器件。 SerDes电路通过恢复时钟将接收的串行数据转换成并行数据，恢复时钟的相位由Ref_SerDes电路生成的相位控制信号P_CS进行控制。 来自脉冲形成电路的偏移脉冲信号Offset_Pulse被施加到相位控制信号P_CS以进行开眼余量测量。
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3.发明授权公开(公告)号：US07443212B2
公开(公告)日：2008-10-28
申请号：US11889098
申请日：2007-08-09
IPC分类号： H03B1/00 , H03K19/0175
CPC分类号： H03K19/018557 , H03K17/163 , H03K17/164 , H03K19/0005 , H03K19/00384 , H03K19/018585
摘要： The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.
摘要翻译： 本发明提供一种半导体集成电路，其可以彼此独立地执行阻抗控制和压摆率控制，并且简化控制电路的结构。 使用包括并联连接的多个输出MOSFET的输出电路，从多个输出MOSFET中，由第一控制装置选择要导通的输出MOSFETS的数量来控制输出阻抗，并且通过第二控制来控制压摆率 意味着控制要导通的输出MOSFET的驱动信号。
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4.发明授权公开(公告)号：US07262643B2
公开(公告)日：2007-08-28
申请号：US11487348
申请日：2006-07-17
IPC分类号： H03B1/00 , H03K19/0175
CPC分类号： H03K19/018557 , H03K17/163 , H03K17/164 , H03K19/0005 , H03K19/00384 , H03K19/018585
摘要： The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.
摘要翻译： 本发明提供一种半导体集成电路，其可以彼此独立地执行阻抗控制和压摆率控制，并且简化控制电路的结构。 使用包括并联连接的多个输出MOSFET的输出电路，从多个输出MOSFET中，由第一控制装置选择要导通的输出MOSFETS的数量来控制输出阻抗，并且通过第二控制来控制压摆率 意味着控制要导通的输出MOSFET的驱动信号。
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5.发明申请公开(公告)号：US20060255842A1
公开(公告)日：2006-11-16
申请号：US11487348
申请日：2006-07-17
IPC分类号： H03K3/00
CPC分类号： H03K19/018557 , H03K17/163 , H03K17/164 , H03K19/0005 , H03K19/00384 , H03K19/018585
摘要： The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.
摘要翻译： 本发明提供一种半导体集成电路，其可以彼此独立地执行阻抗控制和压摆率控制，并且简化控制电路的结构。 使用包括并联连接的多个输出MOSFET的输出电路，从多个输出MOSFET中，由第一控制装置选择要导通的输出MOSFETS的数量来控制输出阻抗，并且通过第二控制来控制压摆率 意味着控制要导通的输出MOSFET的驱动信号。
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公开(公告)号：US20050012533A1
公开(公告)日：2005-01-20
申请号：US10889037
申请日：2004-07-13
IPC分类号： H03K19/0175 , G11C7/00 , H03H11/28 , H03H11/30 , H03K5/22 , H03K17/16 , H03K19/00 , H04L25/02
CPC分类号： H04L25/0278 , H03H11/30
摘要： A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.
摘要翻译： 提供多组电路，每组电路通过与连接到外部端子的电阻元件相关联地使用阻抗控制电路产生阻抗代码，并且每个电路根据这种阻抗代码改变阻抗 。 阻抗控制电路包括阻抗比较器，该阻抗比较器等效于电阻元件和多组电路，并且与多个复制电路中的每一个执行阻抗比较，以形成增加阻抗的向上信号和向下 信号降低阻抗。 提供与多组电路的个体相邻的计数器，从而响应于上升信号和下降信号而产生阻抗代码。
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7.发明授权公开(公告)号：US06835971B2
公开(公告)日：2004-12-28
申请号：US10355006
申请日：2003-01-31
IPC分类号： H01L2710
CPC分类号： H01L27/11 , H01L23/5286 , H01L2224/05001 , H01L2224/05022 , H01L2224/05027 , H01L2224/0508 , H01L2224/05085 , H01L2224/05567 , H01L2224/05572 , H01L2224/16225 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.
摘要翻译： 旨在防止特性劣化的半导体集成电路器件包括通过散射在半导体衬底上以产生一定电压电平的内部电源电压而布置的多个限幅器电路。 每个限幅器电路布置成使其晶体管形成区域位于凸起电极的形成区域正下方，该突起电极放置在外部提供的电源电压中。 限流器电路的分散布局避免了一个限制器电路的电流集中，并减轻了限制器电路及其周边的有害加热。 从凸块电极到晶体管的布线长度越短导致布线电阻越小，减轻布线上的电压降。
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公开(公告)号：US09159904B2
公开(公告)日：2015-10-13
申请号：US14123780
申请日：2012-06-26
申请人： Kenji Nagareda , Atsuhiro Hayashi
发明人： Kenji Nagareda , Atsuhiro Hayashi
IPC分类号： B32B3/02 , H01L41/187 , H01L41/08 , C04B35/495 , C04B35/626
CPC分类号： H01L41/1873 , C04B35/495 , C04B35/6261 , C04B35/62695 , C04B2235/3201 , C04B2235/3203 , C04B2235/3255 , C04B2235/3272 , C04B2235/3294 , C04B2235/3298 , C04B2235/40 , C04B2235/405 , H01L41/0805 , H01L41/1878 , Y10T29/42 , Y10T428/21
摘要： This invention provides for a piezoelectric ceramic composition having a lead-free alkaline niobate piezoelectric ceramic composition with a favorable piezoelectric property. This invention refers to a piezoelectric ceramic composition 10 that is described as composition formula {Lix(K1-yNay)1-x}(Nb1-zSbz)O3 including the additives of the metallic elements Bi and Fe within the range of the following relational expressions: 0.03≦x≦0.045; 0.5≦y≦0.58; 0.03≦z≦0.045; and 0.006≦v≦w≦0.010 whereof v is the additive amount of Bi (molar ratio), and w is the additive amount of Fe (molar ratio).
摘要翻译： 本发明提供一种具有良好压电性能的无铅碱铌酸盐压电陶瓷组合物的压电陶瓷组合物。 本发明涉及一种压电陶瓷组合物10，其被描述为组成式{Lix（K1-yNay）1-x}（Nb1-zSbz）O3），其包括在以下关系式的范围内的金属元素Bi和Fe的添加剂 ：0.03＆nlE; x＆nlE; 0.045; 0.5＆nlE; y＆nlE; 0.58; 0.03＆nlE; z＆nlE; 0.045; 和0.006＆nlE; v＆nlE; w＆nlE; 0.010其中v是Bi的添加量（摩尔比），w是Fe的添加量（摩尔比）。
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公开(公告)号：US20150099085A1
公开(公告)日：2015-04-09
申请号：US14123780
申请日：2012-06-26
申请人： Kenji Nagareda , Atsuhiro Hayashi
发明人： Kenji Nagareda , Atsuhiro Hayashi
IPC分类号： H01L41/187
CPC分类号： H01L41/1873 , C04B35/495 , C04B35/6261 , C04B35/62695 , C04B2235/3201 , C04B2235/3203 , C04B2235/3255 , C04B2235/3272 , C04B2235/3294 , C04B2235/3298 , C04B2235/40 , C04B2235/405 , H01L41/0805 , H01L41/1878 , Y10T29/42 , Y10T428/21
摘要： This invention provides for a piezoelectric ceramic composition having a lead-free alkaline niobate piezoelectric ceramic composition with a favorable piezoelectric property. This invention refers to a piezoelectric ceramic composition 10 that is described as composition formula {Lix(K1-yNay)1-x}(Nb1-zSbz)O3 including the additives of the metallic elements Bi and Fe within the range of the following relational expressions: 0.03≦x≦0.045; 0.5≦y≦0.58; 0.03≦z≦0.045; and 0.006≦v≦w≦0.010 whereof v is the additive amount of Bi (molar ratio), and w is the additive amount of Fe (molar ratio).
摘要翻译： 本发明提供一种具有良好压电性能的无铅碱铌酸盐压电陶瓷组合物的压电陶瓷组合物。 本发明涉及一种压电陶瓷组合物10，其被描述为组成式{Lix（K1-yNay）1-x}（Nb1-zSbz）O3），其包括在以下关系式的范围内的金属元素Bi和Fe的添加剂 ：0.03＆nlE; x＆nlE; 0.045; 0.5＆nlE; y＆nlE; 0.58; 0.03＆nlE; z＆nlE; 0.045; 和0.006＆nlE; v＆nlE; w＆nlE; 0.010其中v是Bi的添加量（摩尔比），w是Fe的添加量（摩尔比）。
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10.发明申请公开(公告)号：US20150042210A1
公开(公告)日：2015-02-12
申请号：US14114273
申请日：2012-06-26
申请人： Kenji Nagareda , Yukai Murai , Atsuhiro Hayashi , Yuichi Maida
发明人： Kenji Nagareda , Yukai Murai , Atsuhiro Hayashi , Yuichi Maida
IPC分类号： B06B1/06 , H01L41/187 , H01L41/29 , H01L41/09
CPC分类号： G01F1/662 , B06B1/0644 , B06B1/0651 , B06B1/067 , G01F1/667 , H01L41/0825 , H01L41/083 , H01L41/09 , H01L41/1132 , H01L41/187 , H01L41/1873 , H01L41/29 , H01L41/313 , Y10T29/42
摘要： An electromechanical transformation device comprises an alkaline niobate piezoelectric ceramic composition and a rigid body adhered onto the major surface of the piezoelectric ceramic composition. The piezoelectric ceramic composition is made of crystal structures such as orthorhombic crystals formed at the side where the temperature is lower than the orthorhombic-to-tetragonal phase transition temperature, tetragonal crystals formed at the side where the temperature is higher than the orthorhombic-to-tetragonal phase transition temperature as well as at the side where the temperature is lower than the tetragonal-to-cubic phase transition temperature, and the cubic crystals formed at the side where the temperature is higher than the tetragonal-to-cubic phase transition temperature. Young's modulus of the rigid body is 60 GPa or more and the volume percent of the piezoelectric ceramic composition existing within a range where the distance from the adhesion point of the piezoelectric ceramic composition and the rigid body is 40% or more.
摘要翻译： 机电转化装置包括碱性铌酸盐压电陶瓷组合物和粘附在压电陶瓷组合物的主表面上的刚体。 该压电陶瓷组合物由温度低于正交相对转变温度的一侧形成的正交晶体等晶体结构构成，在该温度高于斜方晶相的一侧形成四方晶， 四方相转变温度以及温度低于四方相立方相转变温度的一侧，以及形成于温度高于四方相立方相转变温度的一侧的立方晶体。 刚性体的杨氏模量为60GPa以上，压电陶瓷组合物的体积百分比存在于压电陶瓷组合物和刚性体的粘合点的距离为40％以上的范围内。
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