发明授权
US08456946B2 NAND logic word line selection 有权
NAND逻辑字线选择

NAND logic word line selection
摘要:
A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.
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