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    Magnetic tunnel junction ternary content addressable memory
    3.
    发明授权
    Magnetic tunnel junction ternary content addressable memory 有权
    磁隧道结三元内容可寻址存储器

    公开(公告)号：US09543013B1

    公开(公告)日：2017-01-10

    申请号：US15174498

    申请日：2016-06-06

    Applicant: Rekha Govindaraj ,  Swaroop Ghosh

    Inventor： Rekha Govindaraj ,  Swaroop Ghosh

    IPC: G11C15/02 ,  G11C11/16

    CPC classification number: G11C15/02 ,  G11C15/046

    Abstract: A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.

    Abstract translation: 磁性隧道结（MJT）采用六个晶体管的三元内容可寻址存储器（TCAM），并显示出减少的备用泄漏和改进的面积效率。 在所提出的TCAM中，可以通过传统的电流感应磁化技术将数据写入MJT器件，并通过控制源极线，从而消除对外部写入电路的需要。

    Aging-sensitive recycling sensors for chip authentication
    4.
    发明授权
    Aging-sensitive recycling sensors for chip authentication 有权

    公开(公告)号：US10302692B1

    公开(公告)日：2019-05-28

    申请号：US16014195

    申请日：2018-06-21

    Applicant: Swaroop Ghosh ,  Cheng-Wei Lin

    Inventor： Swaroop Ghosh ,  Cheng-Wei Lin

    IPC: G01R31/28 ,  G01R23/02

    Abstract: Various devices, methods and systems are provided for aging-sensitive chip authentication. In one example, among others, a chip includes a reference Schmitt trigger ring oscillator (STRO) configured to enter a sleep mode during operation of the chip; a stressed STRO; a VDD charge pump configured to boost a positive voltage supplied to the stressed STRO during operation of the chip; and/or a GND charge pump configured to under-drive a ground voltage supplied to the stressed STRO during operation of the chip. In another example, a method includes detecting activation of a chip including a reference STRO and a stressed STRO and, in response to the activation of the chip, initiating sleep mode operation of the reference STRO. In response to the activation of the chip, a VDD voltage supplied to the stressed STRO can be boosted and/or a GND voltage supplied to the stressed STRO can be under-driven.

    WIDE OPERATING LEVEL SHIFTERS
    6.
    发明申请
    WIDE OPERATING LEVEL SHIFTERS 有权

    公开(公告)号：US20170237439A1

    公开(公告)日：2017-08-17

    申请号：US15586888

    申请日：2017-05-04

    Applicant: Swaroop Ghosh ,  Kenneth Ramclam

    Inventor： Swaroop Ghosh ,  Kenneth Ramclam

    IPC: H03K19/0185 ,  G11C11/4094 ,  G11C11/408

    CPC classification number: H03K19/018521 ,  G11C11/4087 ,  G11C11/4094 ,  H03K3/012 ,  H03K3/356113

    Abstract: Aspects of wide operating range level shifter designs are described. One embodiment includes a level shifter configured to receive an input signal in a first voltage domain and generate an output signal in a second voltage domain, a pulse generator configured to generate a pulse in response to sensing a rise transition on the input signal, and a droop circuit configured to decouple at least a portion of the level shifter from the second voltage domain in response to the pulse. According to one aspect of the embodiments, the pulse can be provided to the droop circuit to decouple at least a portion of the level shifter from the second voltage domain and reduce contention between transistors in the level shifter. Using the concepts described herein, the worst case rise time delay for level shifters can be significantly reduced.

    MTJ-BASED CONTENT ADDRESSABLE MEMORY
    7.
    发明申请
    MTJ-BASED CONTENT ADDRESSABLE MEMORY 有权
    基于MTJ的内容可寻址存储器

    公开(公告)号：US20170018308A1

    公开(公告)日：2017-01-19

    申请号：US15205813

    申请日：2016-07-08

    Applicant: Swaroop Ghosh ,  Cheng Wei Lin

    Inventor： Swaroop Ghosh ,  Cheng Wei Lin

    IPC: G11C15/04 ,  G11C11/16

    CPC classification number: G11C15/046 ,  G11C11/1675 ,  G11C15/02

    Abstract: Embodiments of the subject invention provide a three transistor, two domain-wall-based magnetic tunnel junction CAM cell (3T-2DW-MTJ CAM). A four transistor, two magnetic tunnel junction ternary CAM cell (4T-2MTJ TCAM) is also provided. An array of the provided CAM cells forms words of various lengths, such as 4-bit, 8-bit, and 16-bit words. Longer CAM words can be formed by an array having hierarchical structures of CAM cells having smaller word sizes, such as 4-bit words or 8-bit words.

    Abstract translation: 本发明的实施例提供三个晶体管，两个基于畴壁的磁隧道结CAM单元（3T-2DW-MTJ CAM）。 还提供了四个晶体管，两个磁性隧道结三元CAM单元（4T-2MTJ TCAM）。 所提供的CAM单元的阵列形成各种长度的字，例如4位，8位和16位字。 较长的CAM字可以由具有较小字长的CAM单元的分层结构的阵列形成，例如4位字或8位字。

    NAND logic word line selection
    8.
    发明授权
    NAND logic word line selection 有权
    NAND逻辑字线选择

    公开(公告)号：US08456946B2

    公开(公告)日：2013-06-04

    申请号：US12928949

    申请日：2010-12-22

    Applicant: Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

    Inventor： Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

    IPC: G11C8/00

    CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

    Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

    Abstract translation: 公开了一种用于在DRAM中选择字线驱动器的NAND架构。 低，中，高范围的分离地址用于选择最终的字线驱动。 字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

    Non-volatile flip-flop with enhanced-scan capability to sustain sudden power failure
    9.
    发明授权
    Non-volatile flip-flop with enhanced-scan capability to sustain sudden power failure 有权

    公开(公告)号：US09728241B2

    公开(公告)日：2017-08-08

    申请号：US15144322

    申请日：2016-05-02

    Applicant: Swaroop Ghosh ,  Anirudh Srikant Iyengar ,  Jae-Won Jang

    Inventor： Swaroop Ghosh ,  Anirudh Srikant Iyengar ,  Jae-Won Jang

    IPC: G11C11/00 ,  G11C11/16 ,  G11C14/00

    CPC classification number: G11C11/1675 ,  G11C14/0081

    Abstract: Non-volatile flip-flops (NVFFs) based circuitries and schemes that incorporate magnetic tunnel junctions (MTJs) are provided to ensure fast data storage and restoration from an intentional or unintentional power outage. The NVFFs based circuitries and schemes also include enhanced scan mode testing capability by exploiting the nonvolatile latch to function as hold latch for delay testing. The NVFFs based circuitries and schemes eliminate additional write drivers, and may operate at an operation frequency of, for example, up to 2 GHz at a supply voltage of 1.1 V and with 0.55 pJ of energy consumption. A near uniform write latency can be achieved through transistor sizing, given write asymmetry of MTJs. NVFFs based circuitries and schemes incorporating data-dependent power gating circuitries can be used to mitigate high static currents generated during retention and back-to-back writing of identical input data.

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