公开(公告)号：US09478273B2

公开(公告)日：2016-10-25

申请号：US14129506

申请日：2013-10-31

Applicant: Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

公开(公告)号：US20140003181A1

公开(公告)日：2014-01-02

申请号：US13997633

申请日：2012-03-30

Applicant: Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC: G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract translation: 描述了一种用于改善存储器单元中的写入裕度的装置和系统。 在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段 的脉冲信号。 在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

公开(公告)号：US20060268626A1

公开(公告)日：2006-11-30

申请号：US11137905

申请日：2005-05-25

Applicant: Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Kim ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  Bo Zheng

Inventor： Fatih Hamzaoglu ,  Kevin Zhang ,  Nam Kim ,  Muhammad Khellah ,  Dinesh Somasekhar ,  Yibin Ye ,  Vivek De ,  Bo Zheng

IPC: G11C7/10

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract translation: 在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。 可以公开和/或要求保护其他实施例。

公开(公告)号：US09455011B2

公开(公告)日：2016-09-27

申请号：US14350997

申请日：2012-03-25

Applicant: Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

Inventor： Arijit Raychowdhury ,  David Kencke ,  Brian Doyle ,  Charles Kuo ,  James Tschanz ,  Fatih Hamzaoglu ,  Yih Wang ,  Roksana Golizadeh Mojarad

IPC: G11C11/00 ,  G11C11/16 ,  G11C5/12 ,  G11C13/00

CPC classification number: G11C11/165 ,  G11C5/12 ,  G11C11/1673 ,  G11C11/1693 ,  G11C2013/0052 ,  G11C2013/0071

Abstract: Methods and systems to read a logic value stored in a magnetic tunnel junction (MTJ)-based memory cell based on a pulsed read current, with time between pulses to permit the MTJ to relax towards the magnetization orientation between the pulses, which may reduce build-up of momentum within the MTJ, and which may reduce and/or eliminate inadvertent re-alignment of a magnetization orientation. A sequence of symmetric and/or non-symmetric pulses may be applied to a wordline (WL) to cause a pre-charged bit line (BL) capacitance to discharge a pulsed read current through the MTJ, resulting in a corresponding sequence of voltage changes on the BL. The BL voltage changes may be integrated over the sequence of read current pulses, and a stored logic value may be determined based on the integrated voltage changes. The pre-charged BL capacitance may also serve as the voltage integrator.

Abstract translation: 基于脉冲读取电流读取存储在基于磁隧道结（MTJ）的存储单元中的逻辑值的方法和系统，脉冲之间的时间允许MTJ朝向脉冲之间的磁化取向松弛，这可以减少构建 - MTJ内的动量，并且其可以减少和/或消除磁化取向的无意重新对准。 对称和/或非对称脉冲的序列可以被施加到字线（WL），以使预充电位线（BL）电容放电通过MTJ的脉冲读取电流，从而产生相应的电压变化序列 在BL上。 可以在读取电流脉冲的序列上积分BL电压变化，并且可以基于积分的电压变化来确定存储的逻辑值。 预充电的BL电容也可以用作电压积分器。

公开(公告)号：US09111600B2

公开(公告)日：2015-08-18

申请号：US13997633

申请日：2012-03-30

Applicant: Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

Inventor： Yih Wang ,  Muhammad M. Khellah ,  Fatih Hamzaoglu

IPC: G11C7/00 ,  G11C5/14 ,  G11C11/413

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C5/148 ,  G11C11/4074 ,  G11C11/412 ,  G11C11/413 ,  G11C11/417

Abstract: Described is an apparatus and system for improving write margin in memory cells. In one embodiment, the apparatus comprises: a first circuit to provide a pulse signal with a width; and a second circuit to receive the pulse signal and to generate a power supply for the memory cell, wherein the second circuit to reduce a level of the power supply below a data retention voltage level of the memory cell for a time period corresponding to the width of the pulse signal. In one embodiment, the apparatus comprises a column of memory cells having a high supply node and a low supply node; and a charge sharing circuit positioned in the column of memory cells, the charge sharing circuit coupled to the high and low supply nodes, the charge sharing circuit operable to reduce direct-current (DC) power consumption.

Abstract translation: 描述了一种用于改善存储器单元中的写入裕度的装置和系统。 在一个实施例中，该装置包括：提供具有宽度的脉冲信号的第一电路; 以及第二电路，用于接收所述脉冲信号并产生用于所述存储器单元的电源，其中所述第二电路将所述电源的电平降低到所述存储单元的数据保持电压电平以下一段对应于所述宽度的时间段 的脉冲信号。 在一个实施例中，该装置包括具有高供应节点和低供应节点的一列存储器单元; 以及位于存储单元列中的电荷共享电路，所述电荷共享电路耦合到所述高电源节点和所述低电源节点，所述电荷共享电路可操作以减少直流（DC）功率消耗。

公开(公告)号：US08456946B2

公开(公告)日：2013-06-04

申请号：US12928949

申请日：2010-12-22

Applicant: Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

Inventor： Swaroop Ghosh ,  Dinesh Somasekhar ,  Balaji Srinivasan ,  Fatih Hamzaoglu

IPC: G11C8/00

CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4087

Abstract: A NAND architecture for selecting a word line driver in a DRAM is disclosed. Separately decoded addresses in the low, mid and high ranges are used to select a final word line driver. The output of the word line driver is at a potential negative with respect to ground for a deselected word line and a positive potential more positive than the power supply potential for a selected word line.

Abstract translation: 公开了一种用于在DRAM中选择字线驱动器的NAND架构。 低，中，高范围的分离地址用于选择最终的字线驱动。 字线驱动器的输出对于取消选择的字线为相对于地的负电位，并且比所选字线的电源电位更正的正电位。

公开(公告)号：US07177176B2

公开(公告)日：2007-02-13

申请号：US10883609

申请日：2004-06-30

Applicant: Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

Inventor： Bo Zheng ,  Kevin Zhang ,  Fatih Hamzaoglu ,  Yih (Eric) Wang

IPC: G11C11/00 ,  G11C5/14 ,  G11C7/10

CPC classification number: G11C11/417 ,  G11C11/412

Abstract: In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (VSSi).

Abstract translation: 在本发明的实施例中，静态随机存取存储器（SRAM）装置具有列和行中的存储器单元阵列。 单个存储单元包括耦合到两个NMOS下拉器件的两个PMOS上拉器件。 在列的READ模式和/或STANDBY / NO-OP模式下，通过正向偏置PMOS n阱或利用较低阈值电压PMOS器件，通过将较低的光晕剂量 PMOS器件。 在列的写入模式下，通过反向偏置PMOS n阱或通过将NMOS器件的源耦合到虚拟接地（V SUB SSi），两个PMOS上拉器件被有效地削弱。

公开(公告)号：US07079426B2

公开(公告)日：2006-07-18

申请号：US10950740

申请日：2004-09-27

Applicant: Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

Inventor： Kevin Zhang ,  Fatih Hamzaoglu ,  Lin Ma

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C5/14 ,  G11C11/413

Abstract: A dynamic multi-voltage memory array features SRAM cells that are subjected to different biasing conditions, depending on the operating mode of the cells. The selected SRAM cell receives a first voltage when a read operation is performed, and receives a second voltage when a write operation is performed. By biasing the cell differently for the two distinct operations, a total decoupling of the read and write operations is achieved. The disclosed memory array, as well as future SRAM designs incorporating the multi-voltage capability thus avoid the conflicting requirements of read and write operations. Random single-bit failures of the memory array are reduced, due to the improvement in read stability and write margin.

公开(公告)号：US06879531B2

公开(公告)日：2005-04-12

申请号：US10324177

申请日：2002-12-19

Applicant: Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

Inventor： Dinesh Somasekhar ,  Yibin Ye ,  Fatih Hamzaoglu ,  Vivek K. De

IPC: G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C7/00 ,  G11C11/00

CPC classification number: G11C7/02 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C2207/2281

Abstract: An offset line to substantially cancel the capacitive coupling effects of a select line to a memory cell. When the select line transitions to cause a stored memory state in the memory cell to be placed onto a sense line, capacitive coupling from the select line to the sense line is substantially cancelled by capacitive coupling, of an opposite polarity, from an offset line to the sense line. Without the opposing effects of the offset line, the capacitive coupling from the select line would raise the pre-charge voltage level on the sense line, which would then require a longer time to discharge down to the input threshold of a sense gate that detects the stored state that was in the memory cell.

Abstract translation: 偏移线，用于基本上消除选择线对存储器单元的电容耦合效应。 当选择线转变以使得存储器单元中存储的存储器状态被放置在感测线上时，从选择线到感测线的电容耦合基本上被相反极性的电容耦合从偏移线到 感觉线。 没有偏移线的相反的影响，来自选择线的电容耦合将提高感测线上的预充电电压电平，这将需要更长的时间来放电到感测门的输入阈值，该感测门检测 存储在存储单元中的状态。

公开(公告)号：US06519176B1

公开(公告)日：2003-02-11

申请号：US09675579

申请日：2000-09-29

Applicant: Fatih Hamzaoglu ,  Ali Keshavarzi ,  Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

Inventor： Fatih Hamzaoglu ,  Ali Keshavarzi ,  Yibin Ye ,  Siva G. Narendra ,  Vivek K. De

IPC: G11C1100

CPC classification number: G11C11/412

Abstract: A six transistor SRAM cell for single-ended sensing is described along with related memory architecture. The cell comprises a bistable circuit connected to complementary bit lines through a pair of passgate transistors. One of the passgate transistors has a lower threshold voltage than the other transistor. The lower threshold voltage is used to couple the cell to a single-ended sense amplifier through one of the bit lines. In one embodiment fewer than all the bit lines in an array are precharged in order to reduce power consumption in the array.

Abstract translation: 描述了用于单端感测的六晶体管SRAM单元以及相关的存储器架构。 该单元包括通过一对通道晶体管连接到互补位线的双稳态电路。 一个通道晶体管具有比另一个晶体管更低的阈值电压。 较低的阈值电压用于通过其中一条位线将单元耦合到单端读出放大器。 在一个实施例中，少于阵列中的所有位线被预充电以便减少阵列中的功耗。