A memory array layout includes an active region array having a plurality of active regions, wherein the active regions are arranged alternatively along a second direction and parts of the side of the adjacent active regions are overlapped along a second direction; a plurality of first doped region, wherein each first doped region is disposed in a middle region; a plurality of second doped region, wherein each second doped region is disposed in a distal end region respectively; a plurality of recessed gate structures; a plurality of word lines electrically connected to each recessed gate structure respectively; a plurality of digit lines electrically connected to the first doped region respectively; and a plurality of capacitors electrically connected to each second doped region respectively.