Invention Grant
US08502324B2 Semiconductor wafer having scribe lane alignment marks for reducing crack propagation
有权
具有用于减少裂纹扩展的划线通道对准标记的半导体晶片
- Patent Title: Semiconductor wafer having scribe lane alignment marks for reducing crack propagation
- Patent Title (中): 具有用于减少裂纹扩展的划线通道对准标记的半导体晶片
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Application No.: US12581549Application Date: 2009-10-19
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Publication No.: US08502324B2Publication Date: 2013-08-06
- Inventor: Victor Pol , Chong-Cheng Fu
- Applicant: Victor Pol , Chong-Cheng Fu
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113 ; H01L31/119

Abstract:
A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.
Public/Granted literature
- US20110089581A1 SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION Public/Granted day:2011-04-21
Information query
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