Semiconductor wafer having scribe lane alignment marks for reducing crack propagation
    1.
    发明授权
    Semiconductor wafer having scribe lane alignment marks for reducing crack propagation 有权
    具有用于减少裂纹扩展的划线通道对准标记的半导体晶片

    公开(公告)号:US08502324B2

    公开(公告)日:2013-08-06

    申请号:US12581549

    申请日:2009-10-19

    Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

    Abstract translation: 提供包括至少第一管芯和至少第二管芯的晶片,其中所述第一管芯和所述第二管芯彼此分开位于所述第一管芯和所述第二管芯之间的区域。 晶片还包括用于将晶片对准用于图案化晶片的工具的对准标记组。 对准标记组完全位于第一管芯和第二管芯之间的区域内,并且对准标记组包括多个对准线,并且其中多个对准线中的每条线使用与每个对准线分离的多个段形成 另外由填充绝缘材料的多个间隙。

    SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION
    2.
    发明申请
    SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION 有权
    具有用于减少裂纹扩展的可选择的对准标记的半导体波形

    公开(公告)号:US20110089581A1

    公开(公告)日:2011-04-21

    申请号:US12581549

    申请日:2009-10-19

    Abstract: A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.

    Abstract translation: 提供包括至少第一管芯和至少第二管芯的晶片,其中所述第一管芯和所述第二管芯彼此分开位于所述第一管芯和所述第二管芯之间的区域。 晶片还包括用于将晶片对准用于图案化晶片的工具的对准标记组。 对准标记组完全位于第一管芯和第二管芯之间的区域内,并且对准标记组包括多个对准线,并且其中多个对准线中的每条线使用与每个对准线分离的多个段形成 另外由填充绝缘材料的多个间隙。

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