发明授权
- 专利标题: Stress enhanced transistor devices and methods of making
- 专利标题(中): 应力增强晶体管器件和制造方法
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申请号: US13419164申请日: 2012-03-13
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公开(公告)号: US08513718B2公开(公告)日: 2013-08-20
- 发明人: Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
- 申请人: Johnathan E. Faltermeier , Judson R. Holt , Xuefeng Hua
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 代理机构: Cantor Colburn LLP
- 代理商 Matthew Zehrer
- 主分类号: H01L29/76
- IPC分类号: H01L29/76
摘要:
A transistor device includes a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.
公开/授权文献
- US20120168775A1 STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING 公开/授权日:2012-07-05