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62 条记录 (耗时 0.019 秒)

    FinFET spacer formation by oriented implantation
    1.
    发明授权
    FinFET spacer formation by oriented implantation 有权
    FinFET间隔物通过定向植入形成

    公开(公告)号：US08716797B2

    公开(公告)日：2014-05-06

    申请号：US12611444

    申请日：2009-11-03

    申请人： Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

    发明人： Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

    摘要： A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

    摘要翻译： 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

    Stress enhanced transistor devices and methods of making
    3.
    发明授权
    Stress enhanced transistor devices and methods of making 有权
    应力增强晶体管器件和制造方法

    公开(公告)号：US08216893B2

    公开(公告)日：2012-07-10

    申请号：US12691170

    申请日：2010-01-21

    申请人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    发明人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7849 ,  H01L29/66636 ,  H01L29/78

    摘要： Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

    摘要翻译： 公开了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：通过栅极电介质在半导体衬底上方间隔开的栅极导体，其中半导体衬底包括在栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中沟道区域包括 栅极导体下方的底切区域; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。

    DRAM having deep trench capacitors with lightly doped buried plates
    4.
    发明授权
    DRAM having deep trench capacitors with lightly doped buried plates 有权
    DRAM具有具有轻掺杂掩埋板的深沟槽电容器

    公开(公告)号：US07923815B2

    公开(公告)日：2011-04-12

    申请号：US11969986

    申请日：2008-01-07

    申请人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    发明人： Geng Wang ,  Kangguo Cheng ,  Johnathan E. Faltermeier ,  Paul C. Parries

    IPC分类号： H01L21/02

    CPC分类号： H01L29/66181 ,  G11C11/404 ,  H01L27/0805 ,  H01L27/10861

    摘要： By controlling buried plate doping level and bias condition, different capacitances can be obtained from capacitors on the same chip with the same layout and deep trench process. The capacitors may be storage capacitors of DRAM/eDRAM cells. The doping concentration may be less than 3E19cm−3, a voltage difference between the biases of the buried electrodes may be at least 0.5V, and a capacitance of one capacitor may be at least 1.2 times, such as 2.0 times the capacitance of another capacitor.

    摘要翻译： 通过控制掩埋板掺杂水平和偏置条件，可以在相同芯片上的电容器中获得不同的电容，具有相同的布局和深沟槽工艺。 电容器可以是DRAM / eDRAM单元的存储电容器。 掺杂浓度可以小于3E19cm-3，掩埋电极的偏压之间的电压差可以至少为0.5V，并且一个电容器的电容可以是至少1.2倍，例如另一个电容器的电容的2.0倍 。

    HIGHLY SCALABLE TRENCH CAPACITOR
    5.
    发明申请
    HIGHLY SCALABLE TRENCH CAPACITOR 有权
    高可伸缩电容器

    公开(公告)号：US20100207245A1

    公开(公告)日：2010-08-19

    申请号：US12689501

    申请日：2010-01-19

    申请人： Kangguo Cheng ,  Anne Marie Ebert ,  Johnathan E. Faltermeier

    发明人： Kangguo Cheng ,  Anne Marie Ebert ,  Johnathan E. Faltermeier

    IPC分类号： H01L29/92 ,  H01L21/02

    CPC分类号： H01L28/40 ,  H01L21/7682 ,  H01L21/76831 ,  H01L27/10861 ,  H01L29/66181

    摘要： An improved trench structure, and method for its fabrication are disclosed. Embodiments of the present invention provide a trench in which the collar portion has an air gap instead of a solid oxide collar. The air gap provides a lower dielectric constant. Embodiments of the present invention can therefore be used to make higher-performance devices (due to reduced parasitic leakage), or smaller devices, due to the ability to use a thinner collar to achieve the same performance as a thicker collar comprised only of oxide (with no air gap). Alternatively, a design choice can be made to achieve a combination of improved performance and reduced size, depending on the application.

    摘要翻译： 公开了一种改进的沟槽结构及其制造方法。 本发明的实施例提供了一种沟槽，其中套环部分具有气隙而不是固体氧化物套环。 气隙提供较低的介电常数。 因此，本发明的实施例可以用于制造更高性能的装置（由于减小的寄生泄漏）或更小的装置，这是由于能够使用更薄的套环来获得与仅由氧化物构成的更厚的套圈相同的性能 没有气隙）。 或者，根据应用，可以进行设计选择以实现改进的性能和减小的尺寸的组合。

    STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING
    6.
    发明申请
    STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING 有权
    应力增强晶体管器件及其制造方法

    公开(公告)号：US20100187578A1

    公开(公告)日：2010-07-29

    申请号：US12691170

    申请日：2010-01-21

    申请人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    发明人： Johnathan E. Faltermeier ,  Judson R. Holt ,  Xuefeng Hua

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7849 ,  H01L29/66636 ,  H01L29/78

    摘要： Stress enhanced transistor devices and methods of fabricating the same are disclosed. In one embodiment, a transistor device comprises: a gate conductor spaced above a semiconductor substrate by a gate dielectric, wherein the semiconductor substrate comprises a channel region underneath the gate conductor and recessed regions on opposite sides of the channel region, wherein the channel region comprises undercut areas under the gate conductor; a stressed material embedded in the undercut areas of the channel region under the gate conductor; and epitaxially grown source and drain regions disposed in the recessed regions of the semiconductor substrate laterally adjacent to the stressed material.

    摘要翻译： 公开了应力增强型晶体管器件及其制造方法。 在一个实施例中，晶体管器件包括：通过栅极电介质在半导体衬底上方间隔开的栅极导体，其中半导体衬底包括在栅极导体下方的沟道区域和沟道区域相对侧上的凹陷区域，其中沟道区域包括 栅极导体下方的底切区域; 嵌入在栅极导体下方的沟道区域的底切区域中的应力材料; 并且外延生长的源极和漏极区域设置在半导体衬底的与应力材料横向相邻的凹陷区域中。

    SEMICONDUCTOR ETCHING METHODS
    7.
    发明申请
    SEMICONDUCTOR ETCHING METHODS 审中-公开
    半导体蚀刻方法

    公开(公告)号：US20090047791A1

    公开(公告)日：2009-02-19

    申请号：US11839681

    申请日：2007-08-16

    申请人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    发明人： David M. Dobuzinsky ,  Johnathan E. Faltermeier ,  Munir D. Naeem ,  William C. Wille ,  Richard S. Wise

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3081 ,  H01L27/10844 ,  H01L27/11

    摘要： A method of etching semiconductor structures is disclosed. The method may include etching an SRAM portion of a semiconductor device, the method comprising: providing a silicon substrate layer, a nitride layer thereover, an optical dispersive layer over the nitride layer, and a silicon anti-reflective coating layer thereover; etching the silicon anti-reflective coating layer using an image layer; removing the image layer; etching the optical dispersive layer while removing the silicon anti-reflective coating layer; etching the optical dispersive layer and the nitride layer simultaneously; and etching the optical dispersive layer, the nitride layer, and the silicon substrate simultaneously.

    摘要翻译： 公开了蚀刻半导体结构的方法。 该方法可以包括蚀刻半导体器件的SRAM部分，该方法包括：提供硅衬底层，其上的氮化物层，氮化物层上的光学色散层和其上的硅抗反射涂层; 使用图像层蚀刻硅抗反射涂层; 去除图像层; 在去除硅抗反射涂层的同时蚀刻光学色散层; 同时蚀刻光学色散层和氮化物层; 并同时蚀刻光学色散层，氮化物层和硅衬底。