发明授权
US08552509B2 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
有权
集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，其它晶体管位于交叉耦合晶体管之间
- 专利标题： Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors
- 专利标题（中）： 集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，其它晶体管位于交叉耦合晶体管之间
-
申请号： US12754384申请日： 2010-04-05
-
公开(公告)号： US08552509B2公开(公告)日： 2013-10-08
- 发明人: Scott T. Becker , Jim Mali , Carole Lambert
- 申请人： Scott T. Becker , Jim Mali , Carole Lambert
- 申请人地址： US CA Los Gatos
- 专利权人： Tela Innovations, Inc.
- 当前专利权人： Tela Innovations, Inc.
- 当前专利权人地址： US CA Los Gatos
- 代理机构： Martine Penilla Group, LLP
- 主分类号： H01L27/092
- IPC分类号： H01L27/092
摘要：
A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
公开/授权文献
信息查询
IPC分类:
