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1.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with two inside positioned gate contacts and two outside positioned gate contacts and electrical connection of cross-coupled transistors through same interconnect layer 有权集成电路包括交叉耦合晶体管，其具有形成在门级特征布局通道内的栅电极，其具有两个内部定位的栅极触点和两个外部定位的栅极触点以及通过相互互连层的交叉耦合晶体管的电连接公开(公告)号：US08785979B2
公开(公告)日：2014-07-22
申请号：US12753776
申请日：2010-04-02
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Each of a number of conductive features within a gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature, with a centerline of each originating rectangular-shaped layout feature aligned in a parallel manner. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. Widths of the first and second p-type diffusion regions are different, such that the first and second PMOS transistor devices have different widths. Widths of the first and second n-type diffusion regions are different, such that the first and second NMOS transistor devices have different widths. The first and second PMOS and first and second NMOS transistor devices form a cross-coupled transistor configuration.
摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 门电极电平区域内的多个导电特征中的每一个由相应的起始矩形布局特征制成，每个起始矩形布局特征的中心线以平行方式排列。 导电特征分别形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一和第二p型扩散区的宽度不同，使得第一和第二PMOS晶体管器件具有不同的宽度。 第一和第二n型扩散区的宽度是不同的，使得第一和第二NMOS晶体管器件具有不同的宽度。 第一和第二PMOS和第一和第二NMOS晶体管器件形成交叉耦合晶体管配置。
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2.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with electrical connection of cross-coupled transistors through same interconnect layer 有权集成电路包括交叉耦合晶体管，其具有形成在栅极级特征布局通道内的栅电极，其具有通过相互互连层的交叉耦合晶体管的电连接公开(公告)号：US08785978B2
公开(公告)日：2014-07-22
申请号：US12753753
申请日：2010-04-02
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10 , H01L27/02 , H01L27/088 , H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.
摘要翻译： 半导体器件包括由在第一和第二p型扩散区域上限定的第一和第二PMOS晶体管以及由第一和第二n型扩散区域限定的第一和第二NMOS晶体管形成的交叉耦合晶体管配置，每个扩散区域 电连接到公共节点。 PMOS和NMOS晶体管的栅极由仅沿第一平行方向延伸的导电特征形成。 第一和第二p型扩散区域中的每一个的至少一部分形成在垂直于第一平行方向延伸的第一公共线上。 第一和第二n型扩散区域相对于第一平行方向以间隔开的方式形成，使得垂直于第一平行方向延伸穿过衬底延伸的单个线的范围与第一和第二n型扩散区域相交 扩散区域。
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3.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications 有权集成电路包括交叉耦合晶体管，其栅极电极形成在具有栅极接触位置规格的栅极级特征布局通道内公开(公告)号：US08742462B2
公开(公告)日：2014-06-03
申请号：US12754103
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10 , H01L27/02 , H01L27/088 , H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： First and second PMOS transistors are defined over first and second p-type diffusion regions. First and second NMOS transistors are defined over first and second n-type diffusion regions. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.
摘要翻译： 第一和第二PMOS晶体管被限定在第一和第二p型扩散区上。 第一和第二NMOS晶体管被限定在第一和第二n型扩散区上。 每个扩散区电连接到公共节点。 栅极电极由导电特征形成，每个导电特征各自限定在与多个平行栅极电极轨道中的一个唯一相关联并限定的任何一个栅极电平通道内。 第一和第二p型扩散区域中的每一个的至少一部分形成在垂直于第一平行方向延伸的第一公共线上。 第一和第二n型扩散区域相对于第一平行方向以间隔开的方式形成，使得不垂直于第一平行方向延伸穿过衬底延伸的单一线的范围与第一和第二n型扩散区域相交 扩散区域。
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4.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within at least twelve gate level feature layout channels 有权集成电路包括具有形成在至少十二个门级特征布局通道内的栅电极的交叉耦合晶体管公开(公告)号：US08669594B2
公开(公告)日：2014-03-11
申请号：US12753740
申请日：2010-04-02
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： First and second p-type diffusion regions, and first and second n-type diffusion regions are formed in a semiconductor device. Each diffusion region is electrically connected to a common node. Gate electrodes of cross-coupled transistors are defined to extend over the diffusion regions in only a first parallel direction, with each gate electrode fabricated from a respective originating rectangular-shaped layout feature. The first and second p-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. At least a portion of the first n-type diffusion region and at least a portion of the second n-type diffusion region are formed over a common line of extent that extends across the substrate perpendicular to the first parallel direction.
摘要翻译： 第一和第二p型扩散区，以及在半导体器件中形成第一和第二n型扩散区。 每个扩散区电连接到公共节点。 交叉耦合晶体管的栅电极被限定为仅在第一平行方向上在扩散区域上延伸，每个栅电极由相应的起始矩形布局特征制成。 第一和第二p型扩散区域相对于第一平行方向以间隔开的方式形成，使得垂直于第一平行方向延伸穿过衬底延伸的单一线的范围与第一和第二p型扩散区域相交 扩散区域。 第一n型扩散区域的至少一部分和第二n型扩散区域的至少一部分形成在垂直于第一平行方向延伸穿过衬底的共同的范围上。
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5.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with other transistors positioned between cross-coupled transistors 有权集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，其它晶体管位于交叉耦合晶体管之间公开(公告)号：US08552509B2
公开(公告)日：2013-10-08
申请号：US12754384
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes conductive features that are each defined within any one gate level channel uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along second and third gate electrode tracks, respectively. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
摘要翻译： 半导体器件包括导电特征，每个导电特征各自被限定在与多个平行栅极电极轨道中的一个栅极电平通道唯一相关联并且沿着多个平行栅极电极轨迹中 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极分别沿着第二和第三栅电极迹线延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。
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6.发明申请Integrated Circuit Including Cross-Coupled Transistors Having Gate Electrodes Formed Within Gate Level Feature Layout Channels With Shared Diffusion Regions on Opposite Sides of Two-Transistor-Forming Gate Level Feature 有权包含交叉耦合晶体管的集成电路，其栅极电极在栅极电平内形成栅极电极特征布局通道，在双晶体管形成栅极电平特征的相对侧上具有共享扩散区域公开(公告)号：US20130146988A1
公开(公告)日：2013-06-13
申请号：US13741305
申请日：2013-01-14
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/092 , G06F17/50
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
摘要翻译： 半导体器件包括栅极电平区域内的导电特征，每个导电特征均由具有平行于第一方向排列的中心线的相应起始矩形布局特征制成。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第一NMOS晶体管器件的栅电极沿着第一栅电极轨道延伸。 第二PMOS和第二NMOS晶体管器件的栅电极沿着第二栅极电极延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。
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7.发明授权Cross-coupled transistor circuit having diffusion regions of common node on opposing sides of same gate electrode track and gate node connection through single interconnect layer 有权交叉耦合晶体管电路具有通过单互连层的相同栅极电极轨道和栅极节点连接的相对侧上的公共节点的扩散区域公开(公告)号：US09081931B2
公开(公告)日：2015-07-14
申请号：US13831742
申请日：2013-03-15
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/088 , G06F17/50 , H01L27/02 , H01L27/092 , H01L23/538 , H01L27/118 , H01L23/498
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
摘要翻译： 第一栅极电平特征形成第一晶体管类型的第一晶体管和第二晶体管类型的第一晶体管的栅电极。 第二栅极电平特征形成第一晶体管类型的第二晶体管的栅电极。 第三栅极电平特征形成第二晶体管类型的第二晶体管的栅电极。 第一和第二晶体管类型的第二晶体管的栅电极通过由线性导电结构形成的电连接彼此电连接。 第一和第二晶体管类型的第二晶体管的栅电极位于第一和第二晶体管类型的第一晶体管的栅电极所位于的栅电极轨道的相对侧上。
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8.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate electrode placement specifications 有权集成电路包括交叉耦合晶体管，其栅极电极形成在具有栅电极放置规格的栅极级特征布局通道内公开(公告)号：US08835989B2
公开(公告)日：2014-09-16
申请号：US12754566
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. The conductive features respectively form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected in part by a first conductor within a first interconnect level. The gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected in part by a second conductor within the first interconnect level. The first PMOS, second PMOS, first NMOS, and second NMOS transistor devices define a cross-coupled transistor configuration having commonly oriented gate electrodes.
摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 导电特征各自定义在与多个平行栅极电极轨道中的一个唯一相关联并且沿着多个平行栅极电极轨迹中的一个限定的任何一个门级通道内。 导电特征分别形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第二NMOS晶体管器件的栅电极部分地由第一互连电平内的第一导体电连接。 第二PMOS和第一NMOS晶体管器件的栅电极部分地由第一互连级内的第二导体电连接。 第一PMOS，第二PMOS，第一NMOS和第二NMOS晶体管器件限定具有共同取向的栅电极的交叉耦合晶体管配置。
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9.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with outer positioned gate contacts 有权集成电路包括交叉耦合晶体管，其栅极电极形成在门级特征布局通道内，具有外部定位的栅极触点公开(公告)号：US08742463B2
公开(公告)日：2014-06-03
申请号：US12754215
申请日：2010-04-05
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10 , H01L27/02 , H01L27/088 , H01L27/092
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes first and second p-type diffusion regions, and first and second n-type diffusion regions that are each electrically connected to a common node. A gate electrode level region is formed in accordance with a virtual grate defined by virtual lines that extend in only a first parallel direction, such that an equal perpendicular spacing exists between adjacent ones of the virtual lines. Conductive features are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of virtual lines of the virtual grate. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and second NMOS transistor devices are electrically connected, and the gate electrodes of the second PMOS and first NMOS transistor devices are electrically connected.
摘要翻译： 半导体器件包括第一和第二p型扩散区，以及第一和第二n型扩散区，其各自电连接到公共节点。 根据由只在第一平行方向延伸的虚拟线限定的虚拟格栅形成栅极电平区域，使得相邻虚拟线之间存在相等的垂直间隔。 导电特征各自定义在与虚拟炉排的多条虚拟线路中的一条唯一相关联并定义的任何一个门级通道内。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS和第二NMOS晶体管器件的栅电极电连接，并且第二PMOS和第一NMOS晶体管器件的栅电极电连接。
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10.发明授权Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with four inside positioned gate contacts having offset and aligned relationships 有权集成电路包括交叉耦合晶体管，其具有形成在栅极级特征布局通道内的栅电极，其具有具有偏移和对准关系的四个内部定位的栅极触点公开(公告)号：US08581304B2
公开(公告)日：2013-11-12
申请号：US12753810
申请日：2010-04-02
申请人： Scott T. Becker , Jim Mali , Carole Lambert
发明人： Scott T. Becker , Jim Mali , Carole Lambert
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , G11C5/06 , G11C11/412 , H01L21/823475 , H01L23/49844 , H01L23/528 , H01L23/5386 , H01L27/0207 , H01L27/0218 , H01L27/088 , H01L27/092 , H01L27/1052 , H01L27/11 , H01L27/1104 , H01L2027/11853 , H01L2027/11875 , H01L2027/11887 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from respective originating rectangular-shaped layout features having its centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS, second PMOS, first NMOS, and second NMOS transistor devices respectively extend along different gate electrode tracks. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
摘要翻译： 半导体器件包括栅极电极区域内的导电特征，每个导电特征各自由相应的起始矩形布局特征制成，其中心线平行于第一方向排列。 导电特征形成第一和第二PMOS晶体管器件的栅极，以及第一和第二NMOS晶体管器件。 第一PMOS，第二PMOS，第一NMOS和第二NMOS晶体管器件的栅电极分别沿着不同的栅电极轨道延伸。 第一组互连导体电连接第一PMOS和第二NMOS晶体管器件的栅电极。 第二组互连导体电连接第二PMOS和第一NMOS晶体管器件的栅电极。 第一组和第二组互连导体在半导体器件的不同级别内横越彼此。
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