Invention Grant
- Patent Title: Process for the vertical interconnection of 3D electronic modules by vias
- Patent Title (中): 三维电子模块垂直互连的过程
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Application No.: US12258060Application Date: 2008-10-24
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Publication No.: US08567051B2Publication Date: 2013-10-29
- Inventor: Christian Val
- Applicant: Christian Val
- Applicant Address: FR Buc Cedex
- Assignee: 3D Plus
- Current Assignee: 3D Plus
- Current Assignee Address: FR Buc Cedex
- Agency: LaRiviere, Grubman & Payne, LLP
- Priority: FR0707557 20071026
- Main IPC: H01K3/10
- IPC: H01K3/10 ; H05K3/30 ; H05K3/10 ; H05K3/02
Abstract:
A process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.
Public/Granted literature
- US20090260228A1 PROCESS FOR THE VERTICAL INTERCONNECTION OF 3D ELECTRONIC MODULES BY VIAS Public/Granted day:2009-10-22
Information query
