公开(公告)号：US09111688B2

公开(公告)日：2015-08-18

申请号：US14115853

申请日：2012-05-04

Applicant: Christian Val

Inventor： Christian Val

IPC: H01G4/224 ,  H05K3/28 ,  H01L21/56 ,  H01L23/00 ,  C23C14/08 ,  C23C16/01 ,  C23C16/40 ,  B05D5/10 ,  B05D1/02 ,  H01L23/31 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01G4/224 ,  B05D1/02 ,  B05D5/10 ,  C23C14/08 ,  C23C16/01 ,  C23C16/402 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/18 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68368 ,  H01L2224/24227 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01079 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/181 ,  H05K1/115 ,  H05K1/181 ,  H05K3/284 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/82

Abstract: A method for collectively fabricating a reconstituted wafer comprising chips exhibiting connection pads on a front face of the chip, comprises: positioning the chips on an initial adhesive support, front face on the support, vapor deposition at atmospheric pressure and ambient temperature, of an electrically insulating layer on the initial support and the chips, having a mechanical role of holding the chips, transfer of the chips covered with the mineral layer onto a provisional adhesive support, rear face of the chips toward this provisional adhesive support, removal of the initial adhesive support, overlaying the chips onto a support of “chuck” type, front faces of the chips toward this support, removal of the provisional adhesive support, deposition of a resin on the support of “chuck” type to encapsulate the chips, and then polymerization of the resin, removal of the support of “chuck” type, production of an RDL layer active face side.

Abstract translation: 一种用于共同制造重构的晶片的方法，其包括在芯片的前表面上显示连接焊盘的芯片，包括：将芯片定位在初始粘合剂支撑体上，支撑体上的正面，大气压和环境温度下的气相沉积 在初始支撑体上的绝缘层和芯片，具有保持芯片的机械作用，将由矿物层覆盖的芯片转移到临时粘合剂支撑体上，将芯片的后表面朝向该临时粘合剂支撑件移除，初始粘合剂的去除 支撑，将芯片叠加到“卡盘”型的支撑件上，朝向该支撑件的芯片的前表面，去除临时粘合剂支撑件，将树脂沉积在“卡盘”型支撑件上以封装芯片，然后聚合 的树脂，去除“卡盘”型的支撑，生产RDL层有源面。

公开(公告)号：US20100276081A1

公开(公告)日：2010-11-04

申请号：US12522426

申请日：2008-01-28

Applicant: Christian Val

Inventor： Christian Val

IPC: B32B37/00

CPC classification number: H01L24/81 ,  H01L23/481 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05647 ,  H01L2224/16105 ,  H01L2224/16108 ,  H01L2224/16146 ,  H01L2224/81224 ,  H01L2224/8184 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30107 ,  Y10T29/49126 ,  Y10T29/49165 ,  Y10T29/49167 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).

Abstract translation: 本发明涉及一种将第一晶片（T1）的电子部件与第二晶片（T2）的电子部件互连的方法，每个晶片具有在厚度方向上穿过晶片的金属化通孔（1）。 该方法包括在第一晶片（T1）的每个通孔（1）上沉积含有溶剂的导电油墨滴（3）; 在第一晶片（T1）的通孔（1）上基本上重叠第二晶片（T2）的第一晶片（T2）的堆叠，使得第二晶片（T2）的通孔（1） 通过加热或施加真空去除包含在液滴（3）中的50至90％的溶剂，以获得糊状油墨; 和糊状墨滴（3）的激光烧结，以在叠置的金属化通孔（1）之间产生电连接（31）。

公开(公告)号：US20090209052A1

公开(公告)日：2009-08-20

申请号：US12438179

申请日：2007-08-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L21/66 ,  G01R31/28

CPC classification number: H01L22/32 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/6836 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68386 ,  H01L2224/73203 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/1461 ,  Y10T29/49004 ,  H01L2924/00

Abstract: The invention relates to the collective fabrication of n 3D module. It comprises a step of fabricating a batch of n dies i at one and the same thin plane wafer (10) of thickness es comprising silicon, covered on one face with electrical connection pads (20), called test pads, and then with a thin electrically insulating layer (4) of thickness ei, forming the insulating substrate provided with at least one silicon electronic component (11) having connection pads (2) connected to the test pads (20) through the insulating layer. The components are encapsulated in an insulating resin (6) of thickness er, filling the spaces between the components, then separated from one another by first grooves (30) with a width L1 and a depth P1 such that ei+er

公开(公告)号：US5461545A

公开(公告)日：1995-10-24

申请号：US305424

申请日：1994-09-13

Applicant: Michel Leroy ,  Christian Val

Inventor： Michel Leroy ,  Christian Val

IPC: H01L21/56 ,  H01L23/28 ,  H01L23/29 ,  H01L23/31 ,  H05K3/28 ,  H05K5/06 ,  H05K1/16

CPC classification number: H05K3/284 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0715 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: According to an embodiment of the invention the discrete or integrated electronic components are encapsulated, each in a package, for example a plastic one; the packages are then mounted on a printed circuit board, for example an epoxy one. The components and board as a whole are covered with a relatively thick first layer consisting of an organic compound and ensuring a levelling function, followed by a second layer such as an inorganic metal compound, the function of which is to ensure the hermetic sealing of the whole.

Abstract translation: 根据本发明的一个实施例，离散或集成的电子部件被封装在每个封装中，例如塑料电子元件; 然后将包装件安装在印刷电路板上，例如环氧树脂。 组件和板整体上覆盖有由有机化合物组成的相对较厚的第一层和确保平整功能，随后是第二层，例如无机金属化合物，其功能是确保气密性 整个。

公开(公告)号：US5400218A

公开(公告)日：1995-03-21

申请号：US27355

申请日：1993-03-08

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L25/00 ,  H01L21/60 ,  H01L21/98 ,  H01L25/065 ,  H05K7/20

CPC classification number: H01L25/50 ,  H01L24/48 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06579 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/12042 ,  H01L2924/14

Abstract: Disclosed is a 3D encapsulation of semiconductor chips, each chip containing for example an integrated circuit, this encapsulation being aimed at optimising heat dissipation by conduction. Connection means are associated with each chip, making it possible to extend the pads of chips towards three sides of the chip, thus leaving the fourth side free. The chips are stacked on one another and then can be connected to heat dissipation means by their fourth side.

Abstract translation: 公开了半导体芯片的3D封装，每个芯片包含例如集成电路，该封装旨在通过传导优化散热。 连接装置与每个芯片相关联，使得可以将芯片的焊盘延伸到芯片的三个侧面，从而使第四面部分自由。 芯片彼此堆叠，然后可以通过其第四面连接到散热装置。

公开(公告)号：US4553020A

公开(公告)日：1985-11-12

申请号：US565042

申请日：1983-12-23

Applicant: Christian Val

Inventor： Christian Val

IPC: H01L23/06 ,  G01P1/02 ,  H01L23/02 ,  H01L23/057 ,  H01L23/26 ,  H01L23/58 ,  H05B1/00

CPC classification number: G01P1/023 ,  H01L23/057 ,  H01L23/26 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152

Abstract: A hermetically sealed encapsulation package for electronic components and integrated or hybrid electronic circuits has a base on which the component or circuit is mounted in the conventional manner and a cover. In one embodiment, the base includes a layer of a material which is able to retain any water molecules which might remain within the package after sealing or which may result from in-leakage from the surrounding atmosphere.

Abstract translation: 用于电子部件和集成或混合电子电路的气密密封封装封装具有以常规方式和盖子安装组件或电路的基座。 在一个实施例中，底座包括能够保持任何水分子的材料层，所述水分子在密封之后可能保持在包装内，或者可能由于从周围大气的泄漏而产生。

公开(公告)号：US4518818A

公开(公告)日：1985-05-21

申请号：US557256

申请日：1984-01-04

Applicant: Jacques Le Ny ,  Christian Val

Inventor： Jacques Le Ny ,  Christian Val

IPC: H01L23/057 ,  H01L23/08 ,  H01L23/10 ,  H01L25/16 ,  H05K5/06

CPC classification number: H01L25/165 ,  H01L23/057 ,  H01L23/08 ,  H01L23/10 ,  H01L2224/48091 ,  H01L2224/49171

Abstract: An encapsulating case or box for hybrid circuits, able to operate in highly pressurized atmosphere, the components of the hybrid circuit being not subject to the action of pressure. For this purpose, said circuit is enclosed in a case taking the plane of the hybrid circuit substrate as the plane of symmetry, two half-shells made from an electrically insulating rigid material being arranged in symmetrical manner on the two faces of the substrate for creating a zero deformation area within the case. The electrical connections between the hybrid circuit and the connecting pins, outside the case and supported by the substrate are provided by flat metal conductors passing in the gluing plane to the substrate of a half-shell.

Abstract translation: 用于混合电路的封装盒或盒子，能够在高度加压的气氛中工作，混合电路的部件不受压力的作用。 为此，所述电路被封装在以混合电路衬底的平面为对称面的壳体中，由电绝缘的刚性材料制成的两个半壳以对称的方式布置在衬底的两个面上，用于产生 一个零变形区域内的情况。 混合电路和连接销之间的电连接在壳体外部并由基板支撑，由平坦的金属导体提供，该金属导体在胶合平面中通过半壳的基板。

公开(公告)号：US4216444A

公开(公告)日：1980-08-05

申请号：US942195

申请日：1978-09-14

Applicant: Claude Vergnolle ,  Christian Val

Inventor： Claude Vergnolle ,  Christian Val

IPC: H01L27/01 ,  H03H7/24 ,  H05K1/00 ,  H05K1/16 ,  H03H7/26

CPC classification number: H03H7/24 ,  H01L27/016 ,  H05K1/0286 ,  H05K1/167

Abstract: A step adjustable attenuator comprising a silicon substrate on one face of which are deposited thin film-type resistors and electrical conductors by which the resistors are interconnected. Contact points are arranged at the periphery of the substrate and connected to the resistors. However, the attenuating sections are not interconnected on the substrate. A conductive pattern prepared from a conductive film forms finger-like leads of which inner portions are bonded to the contact points. By its shape, the pattern ensures the interconnections between the sections and forms two rows of outputs, one for the connections on the printed-circuit board on which is implanted the attenuator and the other being associated with displaceable straps enabling attenuation to be adjusted.

Abstract translation: 一个阶梯可调衰减器，其包括硅衬底，其一面是沉积的薄膜型电阻器和电导体，电阻器通过该电导体相互连接。 接触点布置在基板的周边并连接到电阻器。 然而，衰减部分不在衬底上互连。 由导电膜制成的导电图案形成指状的引线，其内部部分接合到接触点。 通过其形状，该图案确保了部分之间的互连并形成两排输出，一个用于印刷电路板上的连接，其上植入衰减器，另一个与可移位带相关联，使得能够进行衰减。

公开(公告)号：US08567051B2

公开(公告)日：2013-10-29

申请号：US12258060

申请日：2008-10-24

Applicant: Christian Val

Inventor： Christian Val

IPC: H01K3/10 ,  H05K3/30 ,  H05K3/10 ,  H05K3/02

CPC classification number: H01L22/32 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/481 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68368 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2224/73267 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/18162 ,  H01L2924/351 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A process for the vertical interconnection of 3D electronic modules (100), a module comprising a stack of K electronic wafer levels (19) electrically connected together by conductors lying along the direction of the stack that is perpendicular to the plane of a wafer.

Abstract translation: 一种用于3D电子模块（100）的垂直互连的方法，包括通过垂直于晶片平面的堆叠方向电连接在一起的K个电子晶片级（19）的堆叠的模块。

公开(公告)号：US08243468B2

公开(公告)日：2012-08-14

申请号：US11910433

申请日：2006-04-03

Applicant: Christian Val

Inventor： Christian Val

IPC: H01R12/16

CPC classification number: H01L23/4985 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/5387 ,  H01L25/105 ,  H01L2225/1064 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/19041 ,  H05K1/116 ,  H05K1/189 ,  H05K3/3436 ,  H05K2201/09572 ,  H05K2201/09663 ,  H05K2203/041 ,  H05K2203/0455 ,  Y02P70/613 ,  H01L2924/00

Abstract: The invention relates to an electronic module comprising a stack of n packages of predetermined thickness E, which are provided on a lower surface with connection balls of predetermined thickness eb, said connection balls being connected to a printed circuit for interconnecting the package. The printed circuit is placed on the lower surface of the package level with the balls, is drilled with metallized holes, in which the balls are located and to which they are connected, and has a thickness eci less than eb so as to obtain a module with a total thickness not exceeding n (E+10% eb).

Abstract translation: 本发明涉及一种电子模块，其包括具有预定厚度E的n个封装的堆叠，其在具有预定厚度eb的连接球的下表面上提供，所述连接球连接到用于互连封装的印刷电路。 印刷电路被放置在具有滚珠的包装水平的下表面上，钻有金属化的孔，其中滚珠位于其中并且它们被连接，并且具有小于eb的厚度eci以获得模块 总厚度不超过n（E + 10％eb）。