Invention Grant
- Patent Title: MOS devices with improved source/drain regions with SiGe
- Patent Title (中): 具有SiGe源极/漏极区域改善的MOS器件
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Application No.: US13166481Application Date: 2011-06-22
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Publication No.: US08569846B2Publication Date: 2013-10-29
- Inventor: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
- Applicant: Chun-Chieh Lin , Wei-Hua Hsu , Yu-En Percy Chang , Chung Li Chang , Chi-Feng Cheng , Win Hung , Kishimoto Ko
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L29/78
- IPC: H01L29/78
Abstract:
A method includes forming a gate stack over a semiconductor substrate, and forming a first silicon germanium (SiGe) region in the semiconductor substrate and adjacent the gate stack. The first SiGe region has a first atomic percentage of germanium to germanium and silicon. A second SiGe region is formed over the first SiGe region. The second SiGe region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is lower than the first atomic percentage, wherein the first and the second SiGe regions form a source/drain stressor of a metal-oxide-semiconductor (MOS) device.
Public/Granted literature
- US20110256681A1 MOS Devices with Improved Source/Drain Regions with SiGe Public/Granted day:2011-10-20
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